STM32G4: Wrong description of HRTIM_ADCxR registers in RM0440 Rev 9

[simountain]

If I am correct, the descriptions of
 - HRTIM_ADC2R
   -  Bit 22
 - HRTIM_ADC3R
   - Bit 19
   - Bit 13
 - HRTIM_ADC3R
   - Bit 22
   - Bit 13
   - Bit 10
   - Bit 5
   - Bit 4
   - Bit 0
are not correct in the RM.

They all describe trigger event generation but the trigger output in all these seem wrong:
E.g.: HRTIM_ADC2R, Bit 22,
Original Text: "This bit enables the generation of an ADC trigger upon timer C reset and roll-over event, on ADC trigger 1 output."
It should be: "This bit enables the generation of an ADC trigger upon timer C reset and roll-over event, on ADC trigger 2 output."

Also, I want to ask, if this forum is the right place to give feedback on documentation issues?

Best Simon

[Imen.D]

Hello @simountain and welcome to the Community,

Thank you for bringing this issue to our attention.

An internal ticket number 224817 is submitted in order to fix this. 

 

Also, I want to ask, if this forum is the right place to give feedback on documentation issues?

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Yes, this is the right place to share this kind of feedback and report issues. Please feel free to share them with us here.

Thank you for your contributions.