STM32H563 Multi-Controller Architecture – CPU & Memory Margin

[Ibrahimsha]

Hello ST Community,

I am working on an industrial combo vending machine controller system and would like to request a design review / best-practice feedback for an architecture based on STM32H563ZIT6.

System Overview

• MCU: STM32H563ZIT6 @ 200 MHz

• Operation: Industrial application, 24×7 continuous operation

Architecture:

• Main / Process Controller

• Stepper Motor Controller

• DC Load Controller

Each controller uses a dedicated STM32 MCU to separate process logic, real-time motor control, and power load handling.

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1. Main Controller – CPU Load & Memory Utilization

• Multiple interrupt sources (flow sensors, actuator pulses, PWM capture)

• UART RS485 communication @ 115200

• ADC usage with DMA

• Continuous vs process-based CPU load classification

• Worst-case CPU utilization < 20% (**Please check our attached Doc)

• RAM usage ~4.4%, Flash usage ~4% (Build Analyzer)

Question:
From STM best-practice perspective, is this CPU and memory margin considered sufficient for long-term industrial operation?

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2. Stepper Controller Design

• MCU: STM32H563ZIT6

• Stepper driver: DRV8711

• SPI topology under consideration:

  • Single SPI bus with multiple chip-selects

  • Versus multiple SPI buses

Question:
Is a single SPI bus with multiple CS or Multiple SPI bus with Multiple CS an acceptable and recommended approach for this type of application?

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Objective

• Validate MCU selection

• Confirm CPU and memory margins

• Align the design with STM recommended best practices for industrial systems

Any feedback or guidance from ST engineers or experienced users would be greatly appreciated.

Thank you.

[mƎALLEm]

Hello,

1- I'm wondering about the document confidentiality of the first attachment. It's marked as a confidential document. Are you sure to share that in public?

2- The CPU load / memory size depends on your tests and your application we cannot confirm if STM32H563 is 100% suitable for your application. You need to run some tests and make your assessment.

Edit: image removed.

[Ibrahimsha]

Hello,

Thank you for your response and for the clarification.

1. Regarding document confidentiality
   Thank you for pointing this out. You are correct the attachment was marked as confidential and was shared unintentionally. I will edit the post  for public discussion.

2. Regarding CPU load, memory usage, and MCU suitability
   

   To explain my intention in a different way:
   I have already analyzed my application requirements and, based on those requirements, I planned to choose an STM32 controller. The selected part number, STM32H563, provides all the peripherals required by my application and, on paper, fully accommodates my functional needs.

   In my design, I am utilizing a large number of interrupt sources and making extensive use of ADC resources, along with other peripherals such as timers, UART and I²C. From a configuration point of view, the controller supports all of this.

   My main doubt is related to large-scale and long-term usage, where multiple sequences and peripherals operate in parallel.
   The key question I am trying to clarify is:

   • If an application makes full use of ADC resources and a high number of interrupts, along with other peripherals running in parallel, is the STM32H563 architecturally capable of handling this reliably, assuming correct firmware design (DMA usage, interrupt prioritization, efficient ISRs)?

   I understand that final confirmation always depends on application-level testing, which we are planning to perform. However, before moving forward at scale, I would like to understand from STM’s perspective:

   • Whether this usage model is within the intended design capability of the STM32H563 architecture, and

   • Whether there are any recommended references, datasheet sections, application notes, or best-practice guidelines that address this type of high parallel peripheral utilization.

   Your insights on how STM typically approaches such use cases would be very helpful.

   Thank you for your guidance and support.

    

[mƎALLEm]

The architecture makes possible the usage of multiple interrupts in parallel but you need to assess how to configure each interrupt priority according to your constraints.

There is no specific documentation specific to your application but I can suggest you the AN5872 "Introduction to the system architecture and performance in the STM32H5 MCUs"

[Ibrahimsha]

 

Thank you for your support and for sharing the reference. I will analyze this further.

 

[Ibrahimsha]

Hello,

Thank you for your response and clarification.

We understand that CPU load and memory margin are application-dependent and must be assessed empirically through testing, and we appreciate the guidance that CPU utilization should ideally remain below ~75% as a best practice.

Based on your feedback, we would like to align our internal testing and analysis more closely with STM-recommended approaches. To that end, we kindly request clarification on the following points:

1. Are there any STM-provided tools, application notes, or reference examples (CubeIDE, CubeMX, RTOS utilities, trace, profiling, etc.) that you recommend specifically for:

   • Measuring CPU load accurately on STM32H5

   • Profiling runtime memory (stack/heap) usage over long-duration tests

2. For applications with variable runtime load, are there any common pitfalls or observations seen on STM32H5 devices (e.g., interrupt load, DMA contention, cache usage, RTOS configuration) that we should pay special attention to during our evaluation?

3. Would it be possible to get guidance or a short review from a local STM FAE or distributor technical team in India, as this project is planned for large-scale deployment after field trials?

Our intention is to follow a structured and conservative approach to MCU selection, ensuring sufficient margin for long-term and 24/7 operation before moving to mass production.

Please let us know if you require any additional data or test results from our side.

Thank you for your continued support.

[mƎALLEm]

Hello,

You keep asking questions in the same thread. Another thread here.

I suggest you to contact your local FAE to help you in your specific application. I don't think the community is the right place to help you in this kind of support. This is not a dedicated channel of support, it's a public community.

See also the answer in this link.

Thank you for your understanding.