STM32H7R3L8 - SPI NSSP seems to cause SCLK and CS simultaneous state change with CPOL=0, CPHA=1

[Juku80001]

Hello

I am using STM32H7R3L8 MCU and STM32CubeIde v1.19.0. I have an issue where if I was to use SPI4 in Motorola mode together with CPOL=0 and CPHA=1, it works fine. It also works fine when I was to do SPI TX via DMA. Although, as I have the need to have CS inactive between each half-word being sent, I tried using the NSSP option of the SPI, which, when zoomed out on the logic analyzer view, seems to have an issue. Problem is, that at random points during a sequence of 1 half-word size transmits, SCLK and CS sometimes change their states at the same time, causing errors visible on logic analyzer and it seems like the slave device also can not handle that. 

Configuration:

• SPI4 in Motorola master mode

• HAL driver

• DMA transmit

• Hardware NSS control

• CPOL = 0, CPHA = 1 (SPI_PHASE_2EDGE)

• NSS active low

• NSS pulse mode (NSSP) enabled

Is the combination of CPOL=0, CPHA=1 and NSSP not functional? Should I be controlling the CS in software mode instead? Or am I missing something else?

I have also added images of 2 half-word transmits one after another. First working, then error. Slight differences between SCLK and CS timings can be seen.

Thank you in advance

[TDK]

Increase the time between CS low and SCK pulse if the device requires this. Do this by setting MSSI to 1 or higher.

Do that here:

 

[Juku80001]

Thank you for your answer!

I should have mentioned this too at first, but I have already tried both the MSSI and MIDI (just in case) with various values, though none in the range of 0-2 make a difference in the result.

[TDK]

This works for me. Reference manual says it works. I don't know why it would be different for you.

[Juku80001]

Hello! It seems like you are right. After further testing, the problem was logic analyzer sided.