STM32H7RS XSPI HyperBus 16-bit dual mode - how to initialize CR0 of second HyperRAM chip (IO[15:8])

[Happybolt]

Hello,

I have two Winbond W956D8MBYA (64Mb, x8) HyperRAM chips connected
to XSPI1 on STM32H7S3 in dual memory mode (DMM=1):

- Chip #0 → IO[7:0] + DQS0
- Chip #1 → IO[15:8] + DQS1
- Shared: CLK, NCLK, NCS

I need to run at 200 MHz, so I need to configure CR0 on both chips:
- Initial latency = 7 cycles (default is 6, valid only up to 166 MHz)
- Fixed latency (required for dual mode per RM0477)

Problem:
According to RM0477, in HyperBus 16-bit dual mode:
1. Variable latency is not supported (LM bit in XSPI_HLCR must be set)
2. Register space access uses only IO[7:0]. Quote from RM0477:
"IO8 to IO15 being not used but driven by the controller"
So I can only access registers of chip #0.

I also tried MSEL bit in XSPI_CR to switch to IO[15:8] in single mem
HyperBus mode - no effect.

Questions:
1. How to write CR0 to chip #1 connected to IO[15:8]?
2. Is there any way to initialize each chip separately before
switching to dual mode?
3. Does the controller duplicate data on IO[15:8] during register
write in dual mode?

MCU: STM32H7S3
Reference: RM0477 Rev9, section 24 XSPI, 16-bit HyperBus dual mode

Thank you

[KDJEM.1]

Hello @Happybolt and welcome to the community;

 

The variable latency is not supported in dual-octal configuration.

Device B interface signals have exactly the same waveforms as device A ones during the instruction, address, alternate-byte, and dummy-cycles phases. In other words, each device always receives the same instruction and the same address. So, both memory devices must be identical.

 

Thank you.

Kaouthar

[Happybolt]

Follow-up: DMM register read returns B1B2B1B2 instead of expected B1B1B2B2

Thank you for the clarification that both chips receive identical signals in dual mode.

However, I'm confused about the data layout when reading registers in DMM.

My understanding (based on your explanation):

In 16-bit dual mode, both chips receive the same command simultaneously. Each chip drives its own byte lane:

• Chip #0 → IO[7:0]
• Chip #1 → IO[15:8]

Since both chips are identical, IR0 on both should be the same value, for example 0xB1B2. So I would expect the controller to assemble two 16-bit words as:

 

 

Word 0: IO[15:8]=B1 (Chip#1), IO[7:0]=B1 (Chip#0) → 0xB1B1Word 1: IO[15:8]=B2 (Chip#1), IO[7:0]=B2 (Chip#0) → 0xB2B2

Expected buffer (4 bytes): B1 B1 B2 B2

What I actually receive: B1 B2 B1 B2

This looks like data from a single chip repeated twice, not interleaved data from two chips.

My register read command:

 

 

c

XSPI_HyperbusCmdTypeDef cmd = {
 .DataLength = 4,
 .Address = W956X8MBYA_IR0_ADDRESS,
 .AddressWidth = HAL_XSPI_ADDRESS_32_BITS,
 .DQSMode = HAL_XSPI_DQS_ENABLE,
 .DataMode = HAL_XSPI_DATA_8_LINES,
 .AddressSpace = HAL_XSPI_REGISTER_ADDRESS_SPACE,
};

Questions:

1. Is this actually the expected behavior for register reads in 16-bit HyperBus dual mode? Or is something wrong with my setup?

[KDJEM.1]

Hello @Happybolt;

 

What do you mean by DMM register? 

For more information about reading status register and addressing; I recommend you to look at RM0477 Rev9 section Dual-octal configuration.

 

 

 

 

I hope this help you.

Thank you.

Kaouthar

[Happybolt]

Bit 6 DMM: Dual-memory configuration This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity. 0: Dual-memory configuration disabled 1: Dual-memory configuration enabled Note: This bit can be modified only when BUSY = 0.

https://www.st.com/resource/en/reference_manual/rm0477-stm32h7rx7sx-armbased-32bit-mcus-stmicroelectronics.pdf

Thank you for the document. After reading it carefully, I now understand the byte order (B1 B1 B2 B2) correctly.

However, I still have a problem with chip register configuration in dual-memory mode.

What I'm trying to do: Configure CR0 register (address 0x1000U) of W956D8MBYA in XSPI dual-memory (DMM=1) mode.

What I observe: After writing CR0 and reading it back, I always get a value corresponding to IR0 — regardless of which address I use (0x0000, 0x0002, 0x1000, 0x0800, etc.).

What I found in RM0477:

"Command-address phase is always using 8 bits in HyperBus protocol (from IO0-IO7). Only the data is on 16-bit for write or read operations accessing the memory space (from IO0-IO15)."

"For memory register accesses, the data is on 8-bit (from IO0 to IO7, IO8 to IO15 being not used but driven by the controller)."

This suggests that in 16-bit dual-memory HyperBus mode, register space access only works through IO0-IO7 (Chip1), and Chip2 (IO8-IO15) is completely ignored during register access.

Question: Is it possible to configure CR0 registers of both chips in dual-memory mode? If so, how? Do I need to temporarily switch to single 8-bit mode with separate CS# for each chip to initialize the registers?

 

[Happybolt]

Also, I have a question about the wrap size. How should I set it with dual-mem?
I need 32 bytes per cache line, so I set 32 ​​in XSPI and 16 in each RAM?
Or does STM automatically multiply because of dual-mem, and I need 16 in XSPI?