STM32N6 - booting off Quad spi (OTP) settings

[Brenden_PLUS]

Goal boot from a Quad SPI flash

• I shouldn't need to change any OTP settings.  
• Any sNor flash chip connected to XSPIM_P2 that can operated in single spi mode can be booted off from?

 

From my understanding if we want to make a dev board and use a different external memory that is not Octo SPI flash but just Quad SPI flash we shouldn't have to change any of the OTP registers.  

Since

• In sNor flash it starts in single spi mode
  • Then in your FSB you can configure the SPI to your given device(From my understanding)
• There are no OTP registers for Nor flash settings
  • These are all setup in the ROM
• Changing OTP 11 bits (5-8) would force us to loose the ability of Dev up (From my understanding)

 

Most of this info is from the

• How to proceed with boot ROM on STM32N6 MCUs
• https://www.st.com/resource/en/user_manual/um3234-how-to-proceed-with-boot-rom-on-stm32n6-mcus-stmicroelectronics.pdf

 

 

No boot source is programmed in OTP default source is serial NOR

No configuration needed

Default settings for the XSPI from the ROM

Flash is the boot when Boot1 (low) Fairly curtain thats sNor flash.

 

Related question

• https://community.st.com/t5/stm32-mcus-products/any-limits-on-flash-selection-for-stm32n6/td-p/856925

[KDJEM.1]

Hello @Brenden_PLUS ;

 

I advise you to look at How to program the OTP fuse bits in the STM32N6 - STMicroelectronics Community article may help you.

 

Thank you.

Kaouthar

[Brenden_PLUS]

bootrom configuration table

* BOOTSR == boot rom switches

[RomainR.]

Hello @Brenden_PLUS 

Your understanding is correct.
By default, in Flash_Boot mode (BOOT0 = BOOT1 = 0), the STM32N6 BootROM configures XSPI1 on Port 2 in single‑SPI mode with the parameters defined in Table 14 of UM3234. This allows the system to boot and copy a signed FSBL binary into the internal AXISRAM2.

Afterwards, depending on the external NOR Flash memory you plan to use, the final configuration must be performed in your FSBL using the External Memory Manager middleware.

Best regards,

Romain,

[Brenden_PLUS]

Another good register to have is 

• HCONF1 - OTP124

 

If you've system is using any 1v8 on any of the VDDIO lines you should set these registers.  Else you might not be able to boot from flash from your FSB because the FSB set the frequency of the spi to fast for it to boot when the configuration is set for a 3v3 line.