STM32N6 XIP with Quad spi

[Brenden_PLUS]

We have both a very RAM constrained and space constrained board.  So the OctoFlash chips are larger then i would like.  

 

So being able to XIP off a spi flash that only has 4 SPI lanes would be very helpful.  I just don't know the ramifications of something like this. 

 

If we have like 200 Mhz chip flash Chip, in spi 1-4-4.  Will this cause a significant delay?  I'm guessing all these instructions get loaded directly into the instruction cache which is only a few KB of storage.  

 

 

If you think this is a valid option.  Does ST have any parts for this?  If I use a different Flashchip.  Will i have a hard time programming it with the standard ST?

 

Related question

* Limitations of flash 

[Brenden_PLUS]

To program a None standard ST Flash chip your going to need to make a 

• .stldr program

Which is a program that gets loaded onto the ram of a stm32 device to flash the flash chip.  

 

Article about that here. 

• https://community.st.com/t5/stm32-mcus-products/generating-external-loader-stldr-for-specific-hardware/m-p/191166#M40799

 

Projects to help with this

• https://github.com/cturvey/stm32-external-loader
  • Projects for making .stldr
• https://github.com/cturvey/stm32extldr
  • Precompiled loaders