'U5 SBus-via-DCACHE1 connectivity

[waclawek.jan]

Is this connection real?

I don't think so. DCACHE implementation subchapter says:

The DCACHE1 is placed on Cortex®-M33 S-AHB bus, and caches only the external RAM
memory region (OCTOSPI, HSPI, and FMC), in the address range [0x6000 0000:0xAFFF
FFFF] of the memory map.
Indeed, by placing a bus matrix demultiplexing node in front of the DCACHE1, S-AHB bus
memory requests addressing SRAM region or peripherals region (respectively in ranges
[0x2000 0000:0x3FFF FFFF] and [0x4000 0000:0x5FFF FFFF]) are routed directly to the
main AHB bus matrix, and the DCACHE1 is bypassed.

whereas the GFXMMU slave port is at 0x2400'0000.

JW

[mƎALLEm]

Hello @waclawek.jan ,

I do agree with you. I will escalate and get back to you.

It could be a connection related to the Flash (a connection just below) not to that slave port but I need to confirm.

Internal ticket number 225541 for follow-up.

[Bubbles]

Hi @waclawek.jan,

well spotted. It's confirmed to be there by mistake. We'll fix this in next RM revision, probably in few weeks time.

BR,

J