STM32F103 RS-485 only with HSI and HSI calibration?

[asrock70]

Posted on September 08, 2015 at 09:21

It is

a good

idea to use

the

STM32F103

communicating over

RS485

(

38400bps

)

only

HSI

clock? STM32F103 will works in temperature -10 + 50C.

I was looking at

the possibility of

user calibration

HSI

,

too

do not understand

.

ST say.

High-speed internal oscillator of 8 MHz, typically). At 25 °C, the HSI has an accuracy of ±1% typically, this is factory trimed.

T

he accuracy value of the RC frequency increases to the maximum value of -2% - +2,5

%

over temperature. -10 +105C.

It can say, typically error is less than 80kHz.

Maximum error is -160kHz +200kHz

Why is it

then

user triming RCC_CR register step 40kHz and user trimming range +- 640kHz?

[jpeacock]

Posted on September 08, 2015 at 19:33

Asynchronous serial does have some tolerance for mismatched baud rate clocks but you have to make some adjustments to allow for it.  First, keep the baud rate as low as possible.  The faster you go the worse the clock jitter will be.  This shows up as framing or overrun errors caused by bits spilling over into the next frame.

Also, make sure there is a gap between characters so the UART has enough time to synchronize to the next start bit.  Try setting both sides to two stop bits.  This adds an extra bit time for the UART receiver to detect the next start bit.

Remember the accuracy is at the base frequency.  When you use the PLL to multiply the clock the inaccuracy gets multiplied as well.  That 1% at 8MHZ is 8% at 64MHz.

  Jack Peacock

[Tesla DeLorean]

Posted on September 08, 2015 at 21:14

When you use the PLL to multiply the clock the inaccuracy gets multiplied as well.  That 1% at 8MHZ is 8% at 64MHz.

The error magnitude might be 8x bigger, but 1% of 64 is 8x bigger than 1% of 8, it doesn't make it 8%.

[asrock70]

Posted on September 09, 2015 at 07:05

Just the

basic

clock error

is

not

increased

by multiplying.

For example

8MHz with 1% error = 8080000Hz 8080000*8=64640000 this is 64MHz +1% error

[jpeacock]

Posted on September 09, 2015 at 14:16

+/-1% at 8Mhz is 7.92MHz to 8.08MHz.  an 8x multiplier yields a clock anywhere from 63.36 to 64.64MHz, +/- 640KHz or effectively 8x the frequency spread without the PLL.  It's semantics but it is 8% of base frequency error. 

UART timing based on 80KHz vs. 640KHz potential clock jitter is significant.  It's enough that ST won't spec the PLL with HSI to clock at the same multiple as the HSE.  Sure, some dramatic license in interpreting percentages but it illustrates the problem with unstable baud rates.

Aside from all the comments, I have used RC oscillators with the PLL to generate baud rates (not on ST parts though, these were 8051s).  It did work, but the controller had some assistance from an external 48MHz USB SOF clock to keep the RC and PLL stable.  I wouldn't recommend it for ST parts except certain M0+ devices that also use an external RTC crystal to keep the RC stable, and even then there has to be some time for the PLL to sync to the external oscillator.