Invalid addresses of NVIC's registers in "STM32 Cortex-M4 MCUs and MPUs programming manual"

[TPiła.1]

Hi,

Section "4.3.11 NVIC register map" states that the base address of the main NVIC register block is 0xE000E100 and NVIC_ISERx registers starts at offset 0x100 (Table 49. NVIC register map and reset values). The same offset is given in section "4.3.2 Interrupt set-enable register x (NVIC_ISERx)".

The problem is that the correct offset is 0x00 and the corresponding sections for registers ISERx, ICERx, ISPRx, ICPRx, IABRx and IPx provides the offsets' values greater by 0x100 than real values.

The table 45 "NVIC register summary" and CMSIS source code (core_cm4.h declaration of NVIC_Type struct) provide correct values.

[Imen.D]

Hello @Tomasz Piłat​ ,

Thank you for bringing this typo to our attention.

This will be fixed in the coming release of PM0214.

Best Regards,

Imen