STM32Mp257 - DDR4 configuration for swizzle bit

[Vijay_V2225]

Hi Community,

I am working with an STM32MP257  interfaced with 16 bit DDR4 of 2 number (16 bit  * 2  = 32 bit = 1 word). I would like to clarify whether the swizzle bit register values actually affect the DQ pin bit-swapping in hardware.

If they do, I need some guidance on how to determine the correct swizzle bit register values. Are there specific calculations or methods recommended for this ?

I have attached my schematic showing the DQ bit swapping with the processor. Any assistance or reference material would be greatly appreciated

Thank you in advance!!

[Erwan SZYMANSKI]

Hello @Vijay_V2225 ,
Did you already check this DDR configuration Application Note : https://www.st.com/resource/en/application_note/an5723-guidelines-for-ddr-configuration-on-stm32mp2-mpus-stmicroelectronics.pdf ? 

I think it can give you great inputs for all the questions you have concerning DDR configuration.

Kind regards,
Erwan.

[Vijay_V2225]

@Erwan SZYMANSKI Thanks for the reply.