Accessing memory protection unit for cores in MP2

[VO]

Does anyone know how to see and set the cacheable status of memory regions in an MP25x series micro? It is very simple for the H755: you pull up the cores in the Cube, and the MPU fields are all there to fill out. The memory regions outlined in the RIF sections for the MP2 do not seem to offer this option.

 

Thanks

 

[Kevin HUBER]

Hello @VO ,

For the STM32MP25x series, the cacheable status of memory regions is not directly configurable through the RIF sections in STM32CubeMX.

A memory mapping for the OpenSTLinux architecture is available in OP-TEE in the dts file name with "resmem" at the end of the name, for example "stm32mp257f-ev1-ca35tdcid-ostl-resmem.dtsi". You can see a complete mapping which will be used by the OSTL side.

 

If you are talking about the M33 cacheable region, you can normally find the ICACHE and DCACHE configuration in the main.c of the project. For instance, with the project "OpenAMP_TTY_echo", you will see these descriptions in "OpenAMP/OpenAMP_TTY_echo/CM33/NonSecure/Core/Src/main.c":

static void MX_ICACHE_Init(void)
{

 if(HAL_ICACHE_DeInit() != HAL_OK)
 {
 while(1);
 }
 ICACHE_RegionConfigTypeDef pRegionConfig = {0};
 pRegionConfig.TrafficRoute = ICACHE_MASTER2_PORT;
 pRegionConfig.OutputBurstType = ICACHE_OUTPUT_BURST_INCR;
 pRegionConfig.Size = ICACHE_REGIONSIZE_2MB;
 pRegionConfig.BaseAddress = 0x00000000;
 pRegionConfig.RemapAddress = 0x80000000;

And also in the function "MPU_Config" in the same file.

Is it what you are looking for?

Best Regards,

Kevin

[VO]

Thank you for that explanation.

[PatrickF]

Hi @VO 

I agree CubeMx does not offer Cortex-M33 MPU settings. Not sure it is something planned in the future.

 

For Cortex-A35, the Cortex-A processors does not offer MPU, but rather an MMU, which is much more complex than a Cortex-M MPU.
Rationale is that MMU is mandatory to support OS like Linux (address remapping, memory paging, etc..).
MMU requires kbytes of 'tables' (and usually different for each Execution Level) which are stored outside the processor, that is, inside a system memory like the DDR (and for Linux, tables are dynamically updated by the OS itself).

Some of the MMU settings should need to be aligned with RIF (secure regions, etc...). I guess it is not automatic.

Regards.

[VO]

Thank you.