APB5 access in Engineering mode

[SMang.1]

Hi,

Can I access APB5 bus in engineering mode to run I2C4 with I2C4_SCL = PZ4, I2C4_SCL = PZ5?

[PatrickF]

Yes, in engineering mode, RCC is in non-secure mode, as well as all IPs secured by ETZPC (except secrets like ROM or some OTPs which are still protected). Except for memory map restrictions, this stand for Cortex-A7 and Cortex-M4.

[SMang.1]

Thanks @PatrickF​ .

Just to confirm, the clock for APB5 is derived from what core?

[PatrickF]

APB5 (pclk5) root clock usually come from PLL2 (AXI clock) with dedicated sub-dividers.

See product RefMan (e.g. RM0436 for STM32MP157), "Core and busses clock generation" in RCC section.