BSP_EXIT_CRITICAL_SECTION for I2C5 init code for CM4 in STM32MP1

[PVaaz.1]

Hello,

For generating the I2C5 init code, I took the I2C4 discovery kit example and modified it accordingly.

Unlike in I2C4, I see the banks of the I2C_DATA and I2C_CLK are different

I2C5: ( GPIOz and GPIO D)

for I2C4 (GPIOZ):

in the I2C4 code generation, there was this critical section code which is present around the CLK and DATA , since in I2C4 both the gpio banks are same, there was this code,

 /* Configure I2C Tx, Rx as alternate function */

 gpio_init_structure.Pin = DISCO_I2C4_SCL_PIN | DISCO_I2C4_SDA_PIN;

 BSP_ENTER_CRITICAL_SECTION(DISCO_I2C4_SCL_SDA_GPIO_PORT);

 HAL_GPIO_DeInit(DISCO_I2C4_SCL_SDA_GPIO_PORT, gpio_init_structure.Pin);

 BSP_EXIT_CRITICAL_SECTION(DISCO_I2C4_SCL_SDA_GPIO_PORT);

but for I2C5 does it has to be changed for both the GPIO Banks of CLock and data?Is it mandatory?

Please advice.

Best,

Ped

[Olivier GALLIEN]

Hi @PVaaz.1​ ,

BSP_ENTER_CRITICAL_SECTION is an abstraction to Periph_Lock / HSEM.

It prevent simultaneous access from A7 and M4 world at same time.

It's recommended to apply it properly

Olivier