Cannot generate TIM5 global interrupt in STM32MP151

[HMasu.1]

I use STM32MP151CAA3 mounted on my own board.

I want to generate TIM5 global interrupt in Cortex-M4.

​

I have written following code, However, ​TIM5 global interrupt doesn't occurs (TIM5_IRQHandler doesn't be called).

In Keil MDK-ARM Debbuger, I have confirmed following settings are reflected.

​

--TIM5_DIER->UIE = 1

--TIM5_CR1->CEN = 1

​--When TIM5 CNT reach TIM5_ARR value, TIM5_SR->UIF is set.

​

#include "stm32mp1xx_hal.h"
 
void TIM5_Start(void)
{
	TIM_HandleTypeDef m_handleTim5;
	TIM_ClockConfigTypeDef sClockSourceConfig;
	TIM_MasterConfigTypeDef sMasterConfig;
 
	__HAL_RCC_TIM5_CLK_ENABLE();
 
	m_handleTim5.Instance = TIM5;
	m_handleTim5.Init.Prescaler = 41999;
	m_handleTim5.Init.CounterMode = TIM_COUNTERMODE_UP;
	m_handleTim5.Init.Period = 0;
	m_handleTim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
	HAL_TIM_Base_Init(&m_handleTim5);
 
	sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
	HAL_TIM_ConfigClockSource(&m_handleTim5, &sClockSourceConfig);
 
	sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
	sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
	HAL_TIMEx_MasterConfigSynchronization(&m_handleTim5, &sMasterConfig);
 
	HAL_NVIC_EnableIRQ(TIM5_IRQn);
 
	TIM5->ARR = (time * 2) - 1;
	TIM5->EGR |= TIM_EGR_UG;
	TIM5->SR = 0;
	HAL_TIM_Base_Start_IT(&m_handleTim5);
}

For your reference, TIM4 ​ global interrupt does not occurs similarly.

But TIM6 or TIM7 global interrupt occurs without any problems.

​

Is there any missing in above code?

Best Regards.

​

H. Masuda

[TDK]

> m_handleTim5.Init.Period = 0;

With ARR = 0, the timer cannot run.

[HMasu.1]

Hi, @TDK​ 

​

Thank you for your answer.

​

​>With ARR = 0, the timer cannot run.

I'm sorry to be confusing.

Once I set "0" to T​IM5_ARR register in Line 14, I set any required value again in Line 27.

So, after Line 30, the timer is running (I have checked it using Debugger).

However, TIM5 global interrupt doesn't occurs (TIM5_IRQHandler doesn't be called), even though TIM5_SR->UIF flag is set.

Is there any other missing in above code?

Best Regards.

​

H. Masuda

​

[TDK]

Ahh, I didn't see that.

Only a few things need to happen for the interrupt to occur:

• TIM_DIER_UIE bit is set
• TIM_SR_UIF is set
• corresponding NVIC interrupt is enabled
• interrupts are enabled and the update interrupt has enough priority

It's possible there is a typo somewhere, maybe the NVIC interrupt for TIM5_IRQn is wrong or something. Seems low probability. Not sure.