DDR 4 DQ bit swapping on the STM32MP257FAI3

[sanjaysb]

Hi ST,

I'm working with the STM32MP257FAI3 Processor and have some concerns regarding DQ bit swapping between the SoC's DQ lines and the DDR4 RAM DQ lines.

I'm already aware of the guidelines document mentioned in this solution.

From my understanding of the document,

• DQ bits within a byte lane and DQ byte lanes are invariant in a device, allowing for appropriate swapping. However, the DqxLnSel registers should remain at their default values.
• This applies to DDR4, and there is no need to configure DQ bit swapping in arm-trusted-firmware. The DDR firmware and DDRCTRL internal PMU will manage DQ swapping during the initial training.

Can anyone validate my understanding?

Thank you in advance.

[PatrickF]

Hi,

your understanding is right, on DDR4 you could freely swap bits within a byte (i.e. belonging to same DQS and DQM signals). You could also swap bytes (warning than a 16-bit platform should always use byte0 and byte1).

There is no 'contro/status register' inside DDR4 accessible thru Data lanes, so there is no configuration needed at all (even during training) as the memory is providing the read bit value on a same line when written (this sound obvious). Bit numbering on memory side is just matter of putting some names on them. Some control settings inside DDR4 are using address lines as data (please refer to JEDEC).

This is not same for LPDDR4 where some memory control/status register could be read/written thru data bytes, so you should inform the controller of the swapping you have done.

You could also refer to AN5489.

Regards.

[sanjaysb]

Thanks for your replay, it helped clarify my confusion.

I may come back again for other clarifications in this loop. please don't mind