DDR Contention

[nielsenni101]

Hello,

I am running on a stm32mp255dak processor with Linux running on the A35 core and FreeRTOS on the M33 core. I am running the M33 core code out of DDR.

I am seeing an issue where the M33 core performance takes a hit and missed deadlines when the A35 core loads the DDR. The issue is very similar to the one described in this forum. 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1220944/am625-lpddr4-access-priority

 

Does anyone know where to start looking to find the root cause of this issue? I done some investigation into the DDRCTRL registers and tired to mess if the QoS of the A35 core, but that did not seem to make a difference. It seems like the issue is a DDR contention issue between the two cores.

[PatrickF]

Hi @nielsenni101 

I cannot help you for DDR prioritization or else settings .

Maybe a dumb question, is ICACHE and DCACHE enabled on M33 for DDR accesses (I hope so) ?

When your have some hard real time, it would be necessary to have some portion of the code or critical data inside  SRAMs.

Regards.

[nielsenni101]

Hi @PatrickF ,

 

Yes ICACHE and DCACHE is enabled on the M33 core. I have been experimenting with putting some of the critical code into SRAM. So far I have not seen any improvement from that, but I am still in the process of getting more into SRAM (unfortunately the binary is way to big to fit into SRAM). I would expect ICACHE and DCACHE to help here but maybe I am getting a lot of cache misses so it is not really helping? Is there a way to tell if ICACHE and DCACHE are actually helping?

This issue seems to be common to other heterogeneous processor architectures (see the link I made in the OP). So I was hoping that there was a known solution to this issue other then just using SRAM because of the large binary size.