DDR interface usage as SRAM FMC at 32B in STM32MP1

[Linas L]

Hello,

Since we have an outgoing shortage of components, I am trying to figure out what I can use to do complex math calculations to offload from FPGA.

STM32MP1 looks like a good device and could replace STM32H747, but I need a connection to the FPGA register system at very high speed. It does have FMC, but only 16 bits. What I would like to use is a 32b bus, since all of my data is that size.

Is it possible to use a DDR interface for that ? I just need to have 32b of data, address pins, as well as some latch signals like read and write, and maybe clock.

[OlivierK]

Hello Linas L (Community Member),

Unfortunately on the STM32MP1, the DDR interface is used by Linux, running code out of DDR memory, and probably rather complex to emulate from FPGA as it is designed to cope with DDR3, LPDDR2/3 SDRAM memories.

And as you noticed, the FMC is up to 16-bit data on STM32MP15x products.

Regards.

Olivier

[Linas L]

Hello Oliver.

I will use bare metal project without any Linux in this case.

This is DDR3 timing diagram. It looks very simple intgeration with FPGA to take data in or out. All I have to do is to set nearly minimal timing, so I don't waste tame on RAS CAS latency, and just latch data in the correct spot.

Like with STM32H7, I could access DDR memory simple by reading inside microcontroller memory ? and it will automatically generate all the timing s for me, is this still valid for DDR ? I don't need a lof or registers, at most 32, so I could use CAS ( or RAS ) as my address bit inside FPGA ( don't know RAS or CAS is lower in memory map )

I would also need to disable refresh command on DDR controller. Is it possible to do ?

My goal is just FPGA double math coprocessor and high level logic, since it is a bit harder to do in FPGA, and takes secons to do in microcontroler in C

[OlivierK]

Hi Linas L (Community Member)

So please correct me if I am wrong, you want to use the DDR interface as an FMC 32-bit data in order to offload processing from FPGA to the STM32MP1 (to use the STM32MP1 as a coprocessor in bare metal). Again, I would like to help but the DDR i/f has not been designed for this purpose, and at this time we don't support bare metal application on STM32MP15.

Also when you say "Like with STM32H7, I could access DDR memory simple by reading inside microcontroller memory ?"

there isn't any DDR memory inside the STM32MP1, only embedded SRAM. The only potential DDR memory available is through the DDR interface precisely.

Regarding the DDR controller to disable the refresh command, it will require to hack the TF-A source code which I would not recommend to do. The refresh commands are listed in the STM32MP15 reference manual and modes are linked to low power states.