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Michael Schmid
Visitor II
March 5, 2022
Solved

Dear Experts, can I use the DCMI on the STM32MP15x, with the Cortex M4, for an asyncron connected non-camera source?

  • March 5, 2022
  • 2 replies
  • 1818 views

I have to design a system, where a STM32MP157, with its embedded Cortex M4, communicate with other clients over a high-speed serial connection. There should be a 10 : 1 serializer for the MOSI line, and a 1 : 10 deserializer for the MISO line (from the STM32MP15x perspective).

While the transmission from the STM32MP15x via the serializer looks doable with the FMC address lines, I am looking for a reasonable fast way to read the asynchronous data from the deserializer. After I read the app note AN5020 Digital camera interface (DCMI) on STM32 MCUs, I think this could be a way.

The idea is: When data arrive via the deserializer, these are clocked into the DCMI, DMA transfered and a interrupt is generated.

When the DCMI is configured as 8 bit, external syncronized, with 8 Databit, HSYNC and VSYNC and the clock, could this work even with long "blanking peroides" (Where VSYNC indicates no data)?

Question 1: Is there a limit on the length of the blanking periods of the DCMI?

Question 2: Must a permanent PixelClock be provided, or can the PixelClock be off in the blanking periods?

Finally, is there an app note on "misusing" the DCMI for other asynchronous non-camera application?

Thank you in advance for any suggestion.

    This topic has been closed for replies.
    Best answer by PatrickF

    Hi @Michael Schmid​ ,

    I'm not expert of DCMI, but looking at spec, it seems doable with M4 and DMA.

    There is no restriction to stop the clock for long period (PIXCLK is completely async).

    There seem no restriction on sync duration.

    I think few clock cycles are anyway needed at beginning and end of sync periods in order for the HW sequencer to detect the HSYNC and VSYNC transitions.

    Which PIXCLK frequency do you target ?

    Anyway, as those specific behavior cannot be guaranteed (obviously not really tested), I think best should be that you do you own trials using an STM32MP157F-EV1 board which provide a DCMI connector.

    Regards.

    In order to give better visibility on the answered topics, please click on 'Select as Best' on the reply which solved your issue or answered your question. See also 'Best Answers'

    2 replies

    P
    PatrickFAnswer
    Technical Moderator
    March 7, 2022

    Hi @Michael Schmid​ ,

    I'm not expert of DCMI, but looking at spec, it seems doable with M4 and DMA.

    There is no restriction to stop the clock for long period (PIXCLK is completely async).

    There seem no restriction on sync duration.

    I think few clock cycles are anyway needed at beginning and end of sync periods in order for the HW sequencer to detect the HSYNC and VSYNC transitions.

    Which PIXCLK frequency do you target ?

    Anyway, as those specific behavior cannot be guaranteed (obviously not really tested), I think best should be that you do you own trials using an STM32MP157F-EV1 board which provide a DCMI connector.

    Regards.

    In order to give better visibility on the answered topics, please click on 'Select as Best' on the reply which solved your issue or answered your question. See also 'Best Answers'

    M
    Michael SchmidAuthor
    Visitor II
    March 9, 2022

    Hi PatrickF,

    thank you for the answer. I know, that this specific use is not guaranteed and not tested from ST. I just wanted to hear, if there are some obvious no-go's I had not seen before, before we invest in buying boards and time. Your answer not make me confident, to try it with a test boards.

    The parallel clock, here PIXCLK, could be beteween 10 to 80MHz, what will be adjusted to the capability of the STM32 side. I will begin with 10MHz PIXCLK, and then see, how far I can go upwards.

    Thanks for your help.

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