DP83867 phy clock problem (don't bring up)
Hi, I'm Mesut
I'm working STM32MP157C and use DP83867IRRGZ Ethernet Phy in RGMII Mode. There is no 125 MHz from CLK_OUT of DP83867IRRGZ on default mode.
But STM32MP157C need 125 MHz on its PG5 pin. For STM32MP157C we must provide a 125 MHz clock from DP83867IRRGZ or RCC.
I create pll4p -> ethck_k clock 125 MHz follow the https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
. I saw this by calling the "cat /sys/kernel/debug/clk/clk_summary" command on linux.
pll4_p 0 0 0 125000000 0 0 50000
ethptp_k 0 0 0 125000000 0 0 50000
ethck_k 0 0 0 125000000 0 0 50000
But when i "ifconfig eth0 up" write, i'm getting the issue.
Why doesn't the internally set rcc clock run ethernet?
[ 23.523586] stm32-dwmac 5800a000.ethernet: Failed to reset the dma
[ 23.528343] stm32-dwmac 5800a000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 23.537298] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Hw setup failed
What could be the problem?
Best regards.
Mesut Ince
