emmc and OTG question points for STM32MP157AAD3T

[lingwang]

Dear  STM：

        We have the following questions to consult：

         ①Does the PA10 of STM32MP157AAD3T have a pull-up resistance inside the OTG_ID pin function?Do I need an external pull resistor when doing OTG ID function at the same time?If so, what is the resistance value of the external pull-up resistor?

        ②What is the maximum capacity supported by the emmc chip attached to the EMMC interface of STM32MP157AAD3T?

       ③When the emmc interface of STM32MP157AAD3T supports the speed of HS200, what is the power supply mode of the external EMMC chip? Our power supply method is shown in the attached picture, please help evaluate whether it can be satisfied. If not, could you recommend the design schematic diagram of EMMC supporting HS200 speed？

     ④Could you provide the reference design of STM32MP157AAD3T？

     ⑤Is there a development board for STM32MP157AAD3T？

[FBL]

Hello @lingwang 

About the first question, according to the reference manual, section 60.5.1 ID line detection, it is clear that it has integrated pull up resistor. It is used to detect when the ID line is left floating (device).

 

[lingwang]

Dear STM：

       Thank you for your reply. Could you please answer the remaining questions together?

[PatrickF]

@Hi @lingwang 

 

2)

from HW perspective, there is no limitation on the maximum size an eMMC could be.

 

3)

eMMC HS200 is 1.8V IO voltage only (VCCQ), you will have to use VDD=1.8V (as no dedicated power rail for SDMMC2 in this product) or an external level translator. Both are usually not handy.

Please note that STM32MP15x has some limitation on the eMMC usable speed  for HS200 (please refer to Errata Sheet).

So, for eMMC, most people stick VDD=VDDQ=3.3V which is fine for DDR52 (104MBytes/s raw bandwidth).

 

Btw, some comments on your schematics:

- why using PMIC-EA3059+RT9026GFP instead of using STPMIC1A, which is perfectly suited for STM32MP15x (you will probably gain SW development time as all in integrated and tested with this PMIC, especially low power modes) ?

- Why using 26MHz for HSE clock ? We recommend using 24MHz unless absolutely required by your application (you will probably gain SW development time as all in integrated and tested with 24MHz). 26MHz USB boot requires OTP change.

- BOOT pins have internal pull-down and requires only external pull-up (1K recommended)

- with x16 DDR3L, you could remove VTT and termination (lower power and easier DDR routing) which are optional.

 

Maybe look to AN5031 for more recommendations.

 

4) please have a look to AN5122 and as well example in https://www.st.com/resource/en/hw_model/stm32mp15x-series-ddr-memory-routing-guidelines-examples.zip

 

5) there is no development board with 10x10 package, but you could have a look to STM32MP157D-DK1 which could be a good example. You might also find 3rd party suing STM32MP157xAD

 

Regards.

[lingwang]

Dear STM:

        Thank you for your reply!

         My reply to the above points is as follows:

          1)The PMIC-EA3059+RT9026GFP scheme is carried out in accordance with the separation scheme of the design guidance. In the current scheme, can the main chip start up and work normally? If not, what needs to be changed? At the same time to enter the low power mode, the current solution can work?

           2)We use active crystal 24Mhz, sorry for the wrong label.

          3)If we remove the VTT, will the carrier have any other impact because we are more cable-intensive? As for the DDR part, can you help with the simulation after the layout?

[PatrickF]

Hi,

 

1) I cannot answer for this setup. Please have a look to associated application notes
https://www.st.com/resource/en/application_note/an5256-stm32mp151-stm32mp153-and-stm32mp157-discrete-power-supply-hardware-integration-stmicroelectronics.pdf
https://www.st.com/resource/en/application_note/an5089-stm32mp151153157-mpu-lines-and-stpmic1-integration-on-a-wall-adapter-supply-stmicroelectronics.pdf

https://www.st.com/resource/en/application_note/an5109-stm32mp15x-lines-using-lowpower-modes-stmicroelectronics.pdf

 

2) OK

3) please clarify what mean "cable-intensive" (translation issue ?). No specific drawback foresee if AN5122 routing guidelines is followed (impedance, length, etc...). No termination mean slightly lower margin in signal integrity, but DDR3L has been seen as quite robust when used with STM32MP1. You could also do some Signal integrity simulation on your own (please refer to https://www.st.com/resource/en/application_note/an4803-highspeed-si-simulations-using-ibis-and-boardlevel-simulations-using-hyperlynx-si-on-stm32-mcus-and-mpus-stmicroelectronics.pdf )

 

Regards.