eMMC issues on custom board

[OskarM]

Dear All,

I have a total of 8 boards with eMMC from Alliance Memory. All of them boot from SDCard and work well. On 4 of them eMMC is detected correctly and boots fine with 50Mhz/8bit/ddr speed.

4 boards are failing in exactly the same manner, that is:  EXTCSD/CID registers have some wrong values and eMMC is discovered as 128MB (instead of ~4GB), with with wrong manuf. ID and manufacturer code. Writing gives io-error (timeout) - reading returns "ER18" ascii code every 512bytes.

I have lowered down params of sdmmc interface down to: 400kHz / 1 bit / no-ddr, with different slew-rates on IO ports without a success. I've observed these changes on an oscilloscope and also with simple logic analyzer on lower speeds/1bit bus. Failure is persistent between restarts and also between boards. I have also manipulated series resistors and pull-up resistors.

Normally I'd expect some layout issues, but this failure mode is really stable and I am looking for other ideas. I can't imagine that "poorly" soldered part would give the same wrong register values between different PCBs and so consistent between reboots. 

What else could I check except before re-soldering/changing the IC?

Thanks

[PatrickF]

Hi @OskarM 

maybe give more details.

Which STM32MP part

Is the eMMC VCCQ supply is the same than the VDD on STM32MP side (for STM32MP15 not having eMMC dedicate supply rail) ?

Is the eMMC supplied by 3.3V on VCC ?

Is there decoupling on the eMMC VDDI pin ?

Did you play with IO speed settings ? Try reducing it as driving too strongly the PCB line is an usual error.
You could also try to add a serie resistor on the clock line close to STM32MP side ?
Clock signal ringing could lead to weird results, even at lower frequency.

Regards

[Tesla DeLorean]

Power connections? Do you have the ability to X-Ray the board to check for soldering issues?

I've seen mention of "ER 18" pattern in failing cases, but this would likely be coming from the eMMC itself, you might discuss with Alliance as to causal reasons for this or the NAND array to fail.

[OskarM]

Thanks for all the inputs. Below missing info:

Chip: stm32mp153c

Clock has 22Ohm in series, I tried 0Ohm, tried setting slew-rate in dts 0 to 3, I have not tried all combinations of course, but I saw no difference. Other pins had 50Ohm in series (it worked for other boards!!), removed. No difference. Pull-ups 10k on cmd/clk,  other had 50k - removed, left only on D0 (10k). Enabled pullups on the CPU input. Boards that work - need no modifications at all.

All supplies are 3V3, there is a decoupling on the regulator output as well as on digital supply pins.

I got x-ray from the PCB assembly site, but for 2 random boards from the lot, unfortunatelly, so PCBs are not identified. But I could see a very good soldering, balls equally flattened with distinct pad shape, not too much of flux visible. If the process is consistent, then there should be no problem. The DDR and CPU work perectly fine, so it would be really strange to have eMMC not soldred on the same board and side. We'll have x-ray done in a week or two for the failing boards.

Layout is not too good, but I had no chance to modify it beforehand. Tracks have large impedance - I calculated ca 80ohms. There is 1 microvia on the supply pin, while rest is routed with trough hole vias on the other side and docoupled.  Clock and data are not well length aligned, but its minor difference since tracks in general are pretty short. The plane layout is OK. Signal routing is ball-through, as there was no technical capacity to make tracks < 4mils for the 0.5mm pitch. I suppose there are many things that could be improved here, but still - some boards work ok. I can't share layout here, unfortunatelly.

After your suggestions I will try to go in other direction to even further reduce slew-rate. If the 50ohm in D0/D7 works fine for some boards, maybe the clk could have it also in this range.

I have sent questions to Alliance. Waiting for reply.

I have also looked into errata and double checked clocks - sdmmc2_k is 200Mhz form PLL3R.

Thanks!

[OskarM]

So I tried 50Ohm on clk line, with <0> for the slew-rate for clk & data. No difference on 50Mhz and 1Mhz.

I am really out of clue.

Oskar

[PatrickF]

Hi,

Is your Device Tree aligned with wiki example ?

https://wiki.st.com/stm32mpu/wiki/SDMMC_device_tree_configuration#DT_configuration_examples

in particular missing st,neg-edge; might create such kind of issue.

Regards.

 

[OskarM]

One more input from my side: the VCC/VCCQ are both powered from BUCK4 while CPU VDD is powered from BUCK3, for the "A" version of PMIC they are in different ranks, with buck4 being some time later than buck3. I thought that this should be no issue, but maybe it's worth mentioning.

I have seen this power-cycle. I haven't investigated it heavily, because now I can boot from SD, and in linux I can just bind/unbind the driver, which causes re-connection to the mmc without it.

Anyway - thanks again. I think we need to get even lower with investigation.

Best regards