Failing ETH2 on STM32MP2

[jcalvo]

Hi, 
I have a custom board based on STM32MP257FAK3, based on STM32MP257EV1 evaluation board. My board has a rtl8367s ethernet switch connected on eth2 port though rgmii. I can communicate though mdio to the rtl8367s and configure it. We are using OpenWrt kernel and rtl8365mb driver though smi that seems to be the right one.But I can not make works eth2 is failing DMA every time. I will share you my logs and dts. Every idea is welcoming. Thank you!

 

[PatrickF]

HI @jcalvo 

Beside not using OpenSTLinux kernel (I cannot comment on this as I'm not SW expert), the DMA reset error usually mean the GMAC does not receive the 125MHz clock on its internal RX/TX clocks.
There is many options and multiple clocks which could be either from RCC or from PHY, depending on your HW.
All those need to be setup in DTS.
See https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration

 

See also Reference Manual RM0457 to figure out the clocks paths.

 

Regards.

 

[jcalvo]

Hi @PatrickF,

Thank you for your answer. We had reviewed this clock and seems to be active, I attach our clock configuration:

ck_pll6 500000000 Y
ck_flexgen_54 125000000 Y
ck_ker_eth1 125000000 Y
ck_ker_ethsw 125000000 N
ck_flexgen_55 125000000 Y
ck_ker_eth2 125000000 Y

It's really weird because we had used as base image from bootlin https://bootlin.com/blog/openwrt-support-for-stm32mp-updated-and-stm32mp2-added/ . Here they used stm32mp257ev1 as hardware and have both eth1 and eth2 working. We only replace tfa, optee, uboot and dts kernel files. So I can not understand what is changing. As I comment upper our phy RTL8367s is not generating any 125Mhz clock, but it should be generated by pll6. The only difference is that they are using mp257fai and we are using fak3 version. Idk.

Thank you in advance!

root@OpenWrt:~# cat /sys/kernel/debug/clk/stm32_clk_summary
 hardware
 clock rate enable
----------------------------------------------------------------
 hsi_ck 64000000 Y
 ck_pll3 64000000 N
 ck_ker_gpu 64000000 N
 ck_flexgen_08 64000000 Y
 ck_ker_usart2 64000000 N
 ck_ker_uart4 64000000 N
 ck_flexgen_09 64000000 Y
 ck_ker_usart3 64000000 N
 ck_ker_uart5 64000000 Y
 ck_flexgen_19 64000000 Y
 ck_ker_usart1 64000000 N
 ck_flexgen_20 64000000 Y
 ck_ker_usart6 64000000 N
 ck_flexgen_21 64000000 Y
 ck_ker_uart7 64000000 N
 ck_ker_uart8 64000000 N
 ck_flexgen_22 64000000 Y
 ck_ker_uart9 64000000 N
 ck_flexgen_35 16000000 Y
 ck_ker_usbtc 16000000 N
 ck_flexgen_50 64000000 Y
 ck_ker_fmc 64000000 Y
 lsi_ck 32000 Y
 ck_flexgen_41 32000 Y
 ck_ker_lptim4 32000 N
 ck_ker_lptim5 32000 N
 msi_ck 16000000 Y
 ck_flexgen_39 16000000 Y
 ck_ker_lpuart1 16000000 N
 hse_ck 40000000 Y
 hse_div2_ck 20000000 Y
 ck_ker_usb3pciephy 20000000 Y
 ck_hse_rtc 40000000 Y
 ck_pll2 600000000 Y
 ck_pll4 1200000000 Y
 ck_icn_hs_mcu 400000000 Y
 ck_icn_ls_mcu 200000000 Y
 ck_icn_apb1 200000000 Y
 ck_timg1 200000000 Y
 ck_ker_tim2 200000000 N
 ck_ker_tim3 200000000 N
 ck_ker_tim4 200000000 N
 ck_ker_tim5 200000000 N
 ck_ker_tim6 200000000 N
 ck_ker_tim7 200000000 N
 ck_ker_tim10 200000000 N
 ck_ker_tim11 200000000 N
 ck_ker_tim12 200000000 N
 ck_ker_tim13 200000000 N
 ck_ker_tim14 200000000 N
 ck_icn_p_tim2 200000000 N
 ck_icn_p_tim3 200000000 N
 ck_icn_p_tim4 200000000 N
 ck_icn_p_tim5 200000000 N
 ck_icn_p_tim6 200000000 N
 ck_icn_p_tim7 200000000 N
 ck_icn_p_tim10 200000000 N
 ck_icn_p_tim11 200000000 N
 ck_icn_p_tim12 200000000 N
 ck_icn_p_tim13 200000000 N
 ck_icn_p_tim14 200000000 N
 ck_icn_p_lptim1 200000000 N
 ck_icn_p_lptim2 200000000 N
 ck_icn_p_spi2 200000000 N
 ck_icn_p_spi3 200000000 N
 ck_icn_p_spdifrx 200000000 N
 ck_icn_p_usart2 200000000 N
 ck_icn_p_usart3 200000000 N
 ck_icn_p_uart4 200000000 N
 ck_icn_p_uart5 200000000 Y
 ck_icn_p_i2c1 200000000 N
 ck_icn_p_i2c2 200000000 N
 ck_icn_p_i2c3 200000000 N
 ck_icn_p_i2c4 200000000 N
 ck_icn_p_i2c5 200000000 N
 ck_icn_p_i2c6 200000000 N
 ck_icn_p_i2c7 200000000 N
 ck_icn_p_i3c1 200000000 N
 ck_icn_p_i3c2 200000000 N
 ck_icn_p_i3c3 200000000 N
 ck_icn_apb2 200000000 Y
 ck_timg2 200000000 Y
 ck_ker_tim1 200000000 N
 ck_ker_tim8 200000000 N
 ck_ker_tim15 200000000 N
 ck_ker_tim16 200000000 N
 ck_ker_tim17 200000000 N
 ck_ker_tim20 200000000 N
 ck_icn_p_tim1 200000000 N
 ck_icn_p_tim8 200000000 N
 ck_icn_p_tim15 200000000 N
 ck_icn_p_tim16 200000000 N
 ck_icn_p_tim17 200000000 N
 ck_icn_p_tim20 200000000 N
 ck_icn_p_sai1 200000000 N
 ck_icn_p_sai2 200000000 N
 ck_icn_p_sai3 200000000 N
 ck_icn_p_sai4 200000000 N
 ck_icn_p_usart1 200000000 N
 ck_icn_p_usart6 200000000 N
 ck_icn_p_uart7 200000000 N
 ck_icn_p_uart8 200000000 N
 ck_icn_p_uart9 200000000 N
 ck_icn_p_fdcan 200000000 N
 ck_icn_p_spi1 200000000 N
 ck_icn_p_spi4 200000000 N
 ck_icn_p_spi5 200000000 N
 ck_icn_p_spi6 200000000 N
 ck_icn_p_spi7 200000000 N
 ck_icn_apb3 200000000 Y
 ck_icn_p_bsec 200000000 Y
 ck_icn_p_iwdg1 200000000 Y
 ck_icn_p_iwdg2 200000000 N
 ck_icn_p_iwdg3 200000000 N
 ck_icn_p_iwdg4 200000000 N
 ck_icn_p_wwdg1 200000000 N
 ck_icn_p_vref 200000000 N
 ck_icn_p_dts 200000000 N
 ck_icn_p_serc 200000000 Y
 ck_icn_p_hdp 200000000 N
 ck_icn_p_is2m 200000000 N
 ck_icn_apb4 200000000 Y
 ck_icn_p_dsi 200000000 N
 ck_icn_p_ltdc 200000000 N
 ck_icn_p_csi2 200000000 N
 ck_icn_p_dcmipp 200000000 N
 ck_icn_p_ddrc 200000000 Y
 ck_icn_p_ddrcfg 200000000 Y
 ck_icn_p_lvds 200000000 N
 ck_icn_p_gicv2m 200000000 Y
 ck_icn_p_usbtc 200000000 N
 ck_icn_p_usb3pciephy 200000000 Y
 ck_icn_p_stgen 200000000 Y
 ck_icn_p_vdec 200000000 N
 ck_icn_p_venc 200000000 N
 ck_icn_apbdbg 200000000 Y
 ck_sys_dbg 200000000 Y
 ck_icn_p_stm 200000000 N
 ck_icn_p_etr 200000000 N
 ck_icn_s_bkpsram 200000000 Y
 ck_icn_p_ddrphyc 200000000 Y
 ck_icn_p_syscpu1 200000000 Y
 ck_icn_p_hpdma1 200000000 Y
 ck_icn_p_hpdma2 200000000 Y
 ck_icn_p_hpdma3 200000000 Y
 ck_icn_p_ipcc1 200000000 Y
 ck_icn_p_ipcc2 200000000 Y
 ck_icn_p_ipcc2_am 200000000 N
 ck_icn_p_cci 200000000 N
 ck_icn_p_crc 200000000 N
 ck_icn_p_ospiiom 200000000 N
 ck_icn_p_hash 200000000 N
 ck_icn_p_rng 200000000 Y
 ck_icn_p_cryp1 200000000 N
 ck_icn_p_cryp2 200000000 N
 ck_icn_p_saes 200000000 Y
 ck_icn_p_pka 200000000 Y
 ck_icn_p_gpioa 200000000 Y
 ck_icn_p_gpiob 200000000 Y
 ck_icn_p_gpioc 200000000 Y
 ck_icn_p_gpiod 200000000 Y
 ck_icn_p_gpioe 200000000 Y
 ck_icn_p_gpiof 200000000 Y
 ck_icn_p_gpiog 200000000 Y
 ck_icn_p_gpioh 200000000 Y
 ck_icn_p_gpioi 200000000 Y
 ck_icn_p_gpioj 200000000 Y
 ck_icn_p_gpiok 200000000 Y
 ck_icn_s_lpsram1 200000000 Y
 ck_icn_s_lpsram2 200000000 Y
 ck_icn_s_lpsram3 200000000 Y
 ck_icn_p_gpioz 200000000 Y
 ck_icn_p_gpioz_am 200000000 N
 ck_icn_p_lpdma 200000000 N
 ck_icn_p_lpdma_am 200000000 N
 ck_icn_p_adf1 200000000 N
 ck_icn_p_hsem 200000000 N
 ck_icn_p_rtc 200000000 Y
 ck_icn_p_rtc_am 200000000 N
 ck_icn_p_iwdg5 200000000 N
 ck_icn_p_wwdg2 200000000 N
 ck_icn_s_stm 200000000 N
 ck_icn_p_fmc 200000000 Y
 ck_icn_p_eth1 200000000 Y
 ck_icn_p_ethsw 200000000 N
 ck_icn_p_eth2 200000000 Y
 ck_icn_p_pcie 200000000 Y
 ck_icn_p_adc12 200000000 N
 ck_icn_p_adc3 200000000 N
 ck_icn_p_mdf1 200000000 N
 ck_icn_p_spi8 200000000 N
 ck_icn_p_lpuart1 200000000 N
 ck_icn_p_i2c8 200000000 N
 ck_icn_p_lptim3 200000000 N
 ck_icn_p_lptim4 200000000 N
 ck_icn_p_lptim5 200000000 N
 ck_icn_p_risaf4 200000000 Y
 ck_icn_p_i3c4 200000000 N
 ck_ker_eth1stp 200000000 N
 ck_ker_eth2stp 200000000 N
 ck_cpu3 400000000 N
 ck_cpu3_am 400000000 N
 ck_icn_s_sysram 400000000 Y
 ck_icn_s_vderam 400000000 Y
 ck_icn_s_retram 400000000 Y
 ck_icn_s_sram1 400000000 Y
 ck_icn_s_sram2 400000000 Y
 ck_icn_s_ospi1 400000000 Y
 ck_icn_s_ospi2 400000000 Y
 ck_icn_p_otfd1 400000000 Y
 ck_icn_p_otfd2 400000000 Y
 ck_icn_sdmmc 200000000 Y
 ck_icn_m_sdmmc1 200000000 N
 ck_icn_m_sdmmc2 200000000 N
 ck_icn_m_sdmmc3 200000000 N
 ck_icn_ddr 600000000 Y
 ck_icn_s_ddr 600000000 Y
 ck_icn_display 400000000 Y
 ck_icn_hsl 300000000 Y
 ck_icn_m_usb2ohci 300000000 N
 ck_icn_m_usb2ehci 300000000 N
 ck_icn_m_usb3dr 300000000 N
 ck_icn_nic 400000000 Y
 ck_icn_vid 600000000 Y
 ck_flexgen_07 100000000 Y
 ck_ker_lptim1 100000000 N
 ck_ker_lptim2 100000000 N
 ck_flexgen_11 200000000 Y
 ck_ker_spdifrx 200000000 N
 ck_flexgen_12 100000000 Y
 ck_ker_i2c1 100000000 N
 ck_ker_i2c2 100000000 N
 ck_ker_i3c1 100000000 N
 ck_ker_i3c2 100000000 N
 ck_flexgen_13 100000000 Y
 ck_ker_i2c3 100000000 N
 ck_ker_i2c5 100000000 N
 ck_ker_i3c3 100000000 N
 ck_flexgen_14 100000000 Y
 ck_ker_i2c4 100000000 N
 ck_ker_i2c6 100000000 N
 ck_flexgen_15 100000000 N
 ck_ker_i2c7 100000000 N
 ck_flexgen_16 50000000 Y
 ck_ker_spi1 50000000 N
 ck_flexgen_26 100000000 Y
 ck_ker_fdcan 100000000 N
 ck_flexgen_34 20000000 Y
 ck_flexgen_43 50000000 Y
 ck_ker_tsdbg 50000000 Y
 ck_flexgen_44 200000000 Y
 ck_ker_tpiu 200000000 N
 ck_flexgen_45 400000000 Y
 ck_icn_m_etr 400000000 N
 ck_sys_atb 400000000 Y
 ck_flexgen_51 200000000 Y
 ck_ker_sdmmc1 200000000 N
 ck_flexgen_52 200000000 N
 ck_ker_sdmmc2 200000000 N
 ck_flexgen_53 200000000 Y
 ck_ker_sdmmc3 200000000 N
 ck_flexgen_56 200000000 Y
 ck_ker_eth1ptp 200000000 Y
 ck_ker_eth2ptp 200000000 Y
 ck_flexgen_59 600000000 Y
 ck_icn_m_gpu 600000000 N
 ck_flexgen_60 50000000 Y
 ck_ker_ethswref 50000000 N
 ck_flexgen_61 150000000 Y
 ck_mco1 150000000 N
 ck_flexgen_62 150000000 Y
 ck_mco2 150000000 N
 ck_flexgen_63 400000000 Y
 ck_pll5 532000000 Y
 ck_flexgen_17 133000000 Y
 ck_ker_spi4 133000000 N
 ck_ker_spi5 133000000 N
 ck_flexgen_18 133000000 Y
 ck_ker_spi6 133000000 N
 ck_ker_spi7 133000000 N
 ck_flexgen_29 266000000 Y
 ck_ker_csi2 266000000 N
 ck_flexgen_31 26600000 Y
 ck_ker_csi2phy 26600000 N
 ck_flexgen_32 26600000 Y
 ck_ker_lvdsphy 26600000 N
 ck_flexgen_36 133000000 Y
 ck_ker_i3c4 133000000 N
 ck_flexgen_37 133000000 Y
 ck_ker_spi8 133000000 N
 ck_flexgen_38 133000000 Y
 ck_ker_i2c8 133000000 N
 ck_flexgen_46 133000000 Y
 ck_ker_adc12 133000000 N
 ck_flexgen_47 133000000 Y
 ck_ker_adc3 133000000 N
 ck_flexgen_48 133000000 Y
 ck_ker_ospi1 133000000 Y
 ck_flexgen_49 133000000 Y
 ck_ker_ospi2 133000000 Y
 ck_pll6 500000000 Y
 ck_flexgen_54 125000000 Y
 ck_ker_eth1 125000000 Y
 ck_ker_ethsw 125000000 N
 ck_flexgen_55 125000000 Y
 ck_ker_eth2 125000000 Y
 ck_pll7 835511719 Y
 ck_flexgen_10 49147748 Y
 ck_ker_spi2 49147748 N
 ck_ker_spi3 49147748 N
 ck_flexgen_23 49147748 Y
 ck_ker_mdf1 49147748 N
 ck_ker_sai1 49147748 N
 ck_flexgen_24 49147748 Y
 ck_ker_sai2 49147748 N
 ck_flexgen_25 49147748 Y
 ck_ker_sai3 49147748 N
 ck_ker_sai4 49147748 N
 ck_flexgen_42 49147748 Y
 ck_ker_adf1 49147748 N
 ck_pll8 594000000 Y
 ck_flexgen_27 148500000 Y
 ck_ker_ltdc 148500000 N
 ck_flexgen_28 27000000 Y
 clk_phy_dsi 27000000 N
 ck_flexgen_30 20000000 Y
 ck_ker_csi2txesc 20000000 N
 ck_flexgen_33 40000000 Y
 ck_ker_stgen 40000000 Y
 ck_flexgen_57 20000000 Y
 ck_ker_usb2phy1 20000000 N
 ck_flexgen_58 20000000 Y
 ck_ker_usb2phy2 20000000 N
 ck_ker_usb2phy2_en 20000000 N
 ck_ker_dts 40000000 N
 lse_ck 32768 Y
 ck_flexgen_40 32768 Y
 ck_ker_lptim3 32768 N
 ck_rtc 32768 Y
 hsi_ker_ck 64000000 N
 hse_ker_ck 40000000 N
 msi_ker_ck 16000000 N
 ck_ker_i3c4_am 16000000 N
 ck_ker_spi8_am 16000000 N
 ck_ker_i2c8_am 16000000 N
 ck_ker_lpuart1_am 16000000 N
 ck_ker_lptim3_am 16000000 N
 ck_ker_lptim4_am 16000000 N
 ck_ker_lptim5_am 16000000 N
 ck_ker_adf1_am 16000000 N
 spdifsymb 0 Y
 i2sckin 0 Y
 txbyteclk 0 Y
 clk_lanebyte 0 N
 ck_cpu1 0 Y
 ck_c3_adf1 0 N
 ck_c3_gpioz 0 N
 ck_c3_i2c8 0 N
 ck_c3_i3c4 0 N
 ck_c3_lpdma 0 N
 ck_c3_lptim3 0 N
 ck_c3_lptim4 0 N
 ck_c3_lptim5 0 N
 ck_c3_lpuart1 0 N
 ck_c3_rtc 0 N
 ck_c3_spi8 0 N
 ck_obs0 0 Y
 ck_obs1 0 Y
root@OpenWrt:~# ^C

 

[PatrickF]

Hi,

125MHz clock seems enabled, but might not be correctly 'routed' to the ETH2.

https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#RGMII_with_Crystal_on_PHY--no_CLK125_from_PHY_-28Reference_clock_-28standard_RGMII_clock_name-29_CLK125_is_provided_by_a_RCC_SoC_internal_clock-29

 

at first look you might miss at least:

 st,ext-phyclk;

https://github.com/STMicroelectronics/linux/blob/v6.6-stm32mp/Documentation/devicetree/bindings/net/stm32-dwmac.yaml#L88 

Regards. 

[jcalvo]

Hi @PatrickF,

Thank you for your thoughs. We have checked and SYSCFG_ETH2CR is taking value 0x16 instead of 0x17. So ETH2_REF_CLK_SEL is taking 0 as value. Despite we have tryied differents flags from documentation that you had provided nothing changed. Register value continue to be 0x16. We noticed that some flags are marked as obsolet. What are the correct ones? 

Thank you!

&eth2 {
	status = "okay";
	pinctrl-0 = <&eth2_rgmii_pins_a>;
	pinctrl-1 = <&eth2_rgmii_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	/* Probar sin delays primero */
	phy-mode = "rgmii-id";
	max-speed = <1000>;
	
	st,ext-phyclk;
	st,eth-clk-sel;
	st,eth-ref-clk-sel;
	st,eth-ptp-from-rcc;
	
	st,syscon = <&syscfg 0x3400 0x17>;
	
	clock-names = "stmmaceth",
			 "mac-clk-tx",
			 "mac-clk-rx",
			 "ptp_ref",
			 "ethstp",
			 "eth-ck";
		clocks = <&rcc CK_ETH2_MAC>,
			 <&rcc CK_ETH2_TX>,
			 <&rcc CK_ETH2_RX>,
			 <&rcc CK_KER_ETH2PTP>,
			 <&rcc CK_ETH2_STP>,
			 <&rcc CK_KER_ETH2>;
	
	fixed-link {
		speed = <1000>;
		full-duplex;
		pause;
	};
};

  

[PatrickF]

Sorry, It is normal to have ETH2_REF_CLK_SEL=0 in RGMII. forget my previous information.

Maybe check why there is no RX_CLK 125 MHz from the external PHY to the ETH1 (if there is clock on the pin, please check pinmux).

 

in the log, I see some mixed eth2 and eth1, which might be normal, but worth to double check.

I fear I cannot help more.

Regards.

 

[jcalvo]

Hi @PatrickF,

After giving it some thought, we determined that there’s a hardware mistake. Basically, RX and TX are swapped.
We assumed it was the same as the RTL8211F (the other Ethernet controller we have), but according to the datasheet, they’re reversed — what is described as an output on one is an input on the other, and vice versa.

I honestly don’t understand the mess in Realtek’s documentation.

But this must be the problem. We’re going to try swapping the signals, and hopefully tomorrow we’ll have a clearer picture.

Thank you for your effort and time!

[jcalvo]

Hi @PatrickF ,

We confirm that this was the issue. After change rx and tx issue has been solved.

Thank you for your effort.

Best regards,

Javier.

[  16.918752] stm32-dwmac 482d0000.eth2 eth1: Register MEM_TYPE_PAGE_POOL RxQ-0

[  16.920979] stm32-dwmac 482d0000.eth2 eth1: Register MEM_TYPE_PAGE_POOL RxQ-1

[  16.939149] dwmac4: Master AXI performs any burst length

[  16.939233] stm32-dwmac 482d0000.eth2 eth1: No Safety Features support found

[  17.167712] stm32-dwmac 482d0000.eth2 eth1: IEEE 1588-2008 Advanced Timestamp supported

[  17.170379] stm32-dwmac 482d0000.eth2 eth1: registered PTP clock

[  17.176825] stm32-dwmac 482d0000.eth2 eth1: FPE workqueue start

[  17.182197] stm32-dwmac 482d0000.eth2 eth1: configuring for fixed/rgmii-id link mode

[  17.190040] stm32-dwmac 482d0000.eth2 eth1: Link is Up - 1Gbps/Full - flow control rx/tx