FDCAN controller disable receive warn interrupt in stm32mp1

[Ara.1]

do we have any bit disable particular can frame receive warn message as we have in imx6 platform ?

RWRN_MSK

This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error andStatus Register. This bit is read as zero when MCR[WRN_EN] bit is negated. This bit can only be written ifMCR[WRN_EN] bit is asserted.

1Rx Warning Interrupt enabled

0Rx Warning Interrupt disabled

[PatrickF]

Hi,

I'm not CAN specialist, but according to RM0436 (STM32MP157 advanced Arm®-based 32-bit MPUs), there is in FDCAN_IE (together with many other interrupt enable bits)

Bit 24 EWE: Warning status interrupt enable

0: Interrupt disabled

1: Interrupt enabled

[Ara.1]

yes i check this flag but it is generic for tx warn and rx warn message.

i try to send miss can baud from can analyser send, expected not to increase any receive warn.