Hello, I have a question regarding ST marketing on the STM32MP1 devices. According to the page, it states "STM32MP1 users can now choose from several IDEs from leading vendors and enjoy free license"

[PBart.3]

Which IDEs can be used for free in order to download/debug my application in an asynchronous fashion as two cores are running the the same time. I have taken a look on some suppliers (Tools & Software), but it looks like that you need to pay a some money in order to use their eclipse-based IDEs. I mean, how can I evaluate if this MPU family is suitable for our project if I need to invest further money just for a license. I just want to make clear, I am not interested in trail licenses just for testing (limited amout of few kBs ). I would like to know if free IDEs without any bottleneck are available which allow me to develop/port my existing applications into this target? Where can I find it and if applicable where is the corresponding documentation?

thanks

[mleo]

Hello @PBart.3​ ,

What about using dedicated ST tool - STM32CubeIDE?

https://www.st.com/en/development-tools/stm32cubeide.html

It's free, support developements for both M4 and A7 cores, debugging of both cores, etc.

Hope this helps

Regards,

Milan

[Tesla DeLorean]

No, not sure that's how I'd interpret the declaration that's being complained about

https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html

It is like the AND should be capitalized or something, as the two statements seem to be separate, like there are Pro Tools AND there's some other Free Stuff

Now admittedly if you're building LINUX there's a whole bunch of Free GNU/GCC tools to build the kernel, but the OP looks to want to use a Bare Metal approach with two cores, and I'm not seeing free stuff from Keil or IAR

[Tesla DeLorean]

[PBart.3]

Hello @mleo​ ,

Thanks for your reply. Just to make sure that I understood you correctly. Is it correct that the dedicated ST tool called STM32CubeIDE is able to start a debugging session where I can stop the Cortex A7 along with the Cortex M4 simoultanously or asynchronously. So it is up to me if you want to let the Cortex A7 run for some time till a HW breakpoint is hit while the Cortex M4 is paused during that time. So I could decide whether I start to step through the Cortex A7 instructions and then depending on my mood I can switch to the Cortex M4 to single step while the Cortex A7 is paused or running at the same time. The same is applicable the other way around.

Such a debugging behavior is applicable on the STM32CubeIDE debugger?

[PBart.3]

Hello @Community member​ ,

thanks for your input.

This is the description I have found from Arm DS (Development Studio) regarding its capabilites on the page:

"For users who are developing software for both the Cortex-A and Cortex-M, then Development Studio, which can support all Arm processors, is an excellent choice. The Arm Debugger provides the capability to simultaneously debug all Arm processors in the heterogenous device. This tool can be used for kernel and device driver development, as well as Linux application debug via gdbserver. It can also be used for RTOS and bare-metal development on any CPU in the system."

In one of the demonstration from Ac6 (SystemWorkbench4Linux) for the STM32MP1 (debugging both cores), I have seen following scenario:

Dummy data is shifted between both Cores (Cortex-A7 and Cortex-M4) as there is an integrated HW feature for processing intercommunication protocols (IPC).

This was illustrated via the debug session (see picture below):

Something like this is achievable on the STM32CubeIDE as shown above?

I am asking myself what kind of approach you need to take if you plan to integrate own primitve kernel drivers etc. on the Cortex-A7 and you want to debug it efficiently?

[PBart.3]

So what is the conclusion for this question asked above?

[mleo]

Hi @PBart.3​ ,

two concurrent debug sessions in one instance of CubeIDE are possible, see:

https://community.st.com/s/question/0D50X0000Byue7DSQQ/regression-with-cubeide-v120-breakpoint-ignored-

Some hints how to establish the debug sessions:

https://community.st.com/s/question/0D53W000003K9uVSAS/how-to-setup-eclipse-for-for-cross-compilation-and-cross-debugging

https://community.st.com/s/question/0D53W000004HK91SAG/how-to-connect-and-debug-cortexa7-cores-on-stm32mp157cdk2

In latest CubeIDE you don't have to create new ssh connection, done automatically.

Best regards,

Milan

[JCarl.1]

STM32CubeIDE is just a modified version of Eclipse designed specifically for microcontroller development. There's no reason you can't launch multiple debug sessions concurrently, each connecting to a different GDB server under the hood, which would connect to a different core. And even if it didn't support that, you could just fire up two instances of the IDE, and connect each one to a different core and it would be the same experience. So, you're fixating on something that doesn't really matter.

The broader question is whether you really understand what you're getting into. STM32CubeIDE has no out-of-the-box support for bare-metal Cortex-A7 development (nor does ST provide a bare-metal SDK, as far as I know), and it's not like it magically hooks into a Linux kernel source tree and cross-compiler toolchain to build things. So you'll have to manually set all that up if you want to build a Linux kernel / kernel modules from within STM32CubeIDE, and they may have removed/altered some of the "stock" Eclipse options necessary to do that (I haven't checked).

OK, you've got stuff built, now what? No IDE I've seen (free or paid) will automagically deal with relocated addresses, kernel module virtual address space translations, etc. If you're coming from an MCU background, and you expect to go to some hypothetical File > New Kernel Module... menu and start debugging, you've got a long road ahead. You've got to have intimate knowledge of how virtual and physical memory is mapped on your system, and how to coax GDB into dealing with that. It's not the end of the world, but I bet if you asked most developers, they'd tell you that if they had to break out the JTAG adapter to work through a kernel module bug, they're having a pretty bad day.

[PBart.3]

Hello @mleo​ and @Community member​ 

thanks for your feedback. So it is not possible to initialize and assign some generic timers (e.g. Tick interrupt or pwm callback) on the Cortex A7 as we have access to these peripherals and debug it concurrently with the Cortex-M4 while the Cortex M4 is using its own context with some dedicated interupt lines? If no, what is the purpose of STM32CubeMX when you acitivate something (e.g. Analog inputs, Timers ) just for the Cortex A7 context? Code is initialized for the Cortex A7 but you cannot use it? You need to hope that the linux distribution you are using is supporting that component driver in order to use it properly?

[JCarl.1]

Activating and configuring components on the A7 side will trigger STM32CubeIDE to generate DTS code that configures the peripherals accordingly, just like on any other embedded Linux system running on an Arm chip. The Linux kernel modules for each peripheral parses the device tree and configures themselves. You then interact with the peripherals using typical Linux subsystems.

More specifically, you mentioned tick interrupts and PWM callbacks on the A7. Linux has timer callbacks built into the kernel. I've never seen PWM toggle/reload/etc IRQs used in Linux, mainly because Linux IRQ latency is so bad. If the existing Linux PWM / IIO / HRTIMER subsystem is inadequate for your needs, considering doing it on the M4 core.