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SScar.2
Graduate II
May 24, 2024
Solved

How to write STM32MP153 registers (RCC_RDLSICR)?

  • May 24, 2024
  • 1 reply
  • 2673 views

Hi, 

I'm trying to change the value of the register RCC_RDLSICR (RCC reset duration and LSI control register, address offset 0x144). I need to change the Minimum Reset Duration value.

In all power management/low power handling manuals for STM32MP15x lines the documentation says that you can change the registers value, but I can't find HOW I can achieve that. 

I can write them in dts? inside u-boot? please I need clarifications about that. 

NOTE: I'm using a custom STM32MP153 board with OpenSTLinux distribution on it. 

 

Thanks a lot

    This topic has been closed for replies.
    Best answer by SScar.2

    Got IT!! 

    ---
 plat/st/stm32mp1/bl2_plat_setup.c | 10 +++++++---
 plat/st/stm32mp1/stm32mp1_ssp.c | 10 +++++++---
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 6232d7b..795cefe 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -286,10 +286,14 @@ void bl2_el3_plat_arch_setup(void)
 	}
 
 	/* Set minimum reset pulse duration to 31ms for discrete power supplied boards */
-	if (dt_pmic_status() <= 0) {
-		mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
+	// if (dt_pmic_status() <= 0) {
+	// 	mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
+	// 			 31U << RCC_RDLSICR_MRD_SHIFT);
+	// }
+
+	//SS set minimum reset pulse duration MDR register to 31 ms for ALL configurations 
+	mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
 				 31U << RCC_RDLSICR_MRD_SHIFT);
-	}
 
 	generic_delay_timer_init();
 
diff --git a/plat/st/stm32mp1/stm32mp1_ssp.c b/plat/st/stm32mp1/stm32mp1_ssp.c
index 14ce023..9900672 100644
--- a/plat/st/stm32mp1/stm32mp1_ssp.c
+++ b/plat/st/stm32mp1/stm32mp1_ssp.c
@@ -927,10 +927,14 @@ void bl2_el3_plat_arch_setup(void)
 	}
 
 	/* Set minimum reset pulse duration to 31ms for discrete power supplied boards */
-	if (dt_pmic_status() <= 0) {
-		mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
+	// if (dt_pmic_status() <= 0) {
+	// 	mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
+	// 			 31U << RCC_RDLSICR_MRD_SHIFT);
+	// }
+
+	//SS set minimum reset pulse duration MDR register to 31 ms for ALL configurations 
+	mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, RCC_RDLSICR_MRD_MASK,
 				 31U << RCC_RDLSICR_MRD_SHIFT);
-	}
 
 	generic_delay_timer_init();
 
-- 
2.25.1

     I patched both bl2_plat_setup.c and stm32mp1_ssp.c and it works (yes, I bypassed the check of the pmic status/mode), now when I reset the board I can see 31ms on the signal. 

    1 reply

    P
    PatrickF
    Technical Moderator
    May 24, 2024

    Hi @SScar.2 

    I think you have to adapt TF-A code.

    I found some lines related to non-STPMIC case which modify this register.

    https://github.com/STMicroelectronics/arm-trusted-firmware/blob/v2.8-stm32mp/plat/st/stm32mp1/bl2_plat_setup.c#L291

    Regards,

    S
    SScar.2Author
    Graduate II
    May 24, 2024

    Hi Patrick, 

    thanks for the quick response! 

    Our solution adopts STPMIC. I don't know if this is useful information... 

    I could patch the TF-A, but please specify which file I should modify. I'm pretty new to tf-a and I never patched it.

    Thanks again

     

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