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Visitor II
September 16, 2022
Solved

I created DTS files for my custom board, my DDR configuration is same as stm32mp157A-ev1 board and I am using same mpu. Why some of the CUBEMX generated TF-A DDR registers and Eval registers are different?

  • September 16, 2022
  • 1 reply
  • 906 views
EVAL BOARD (stm32mp15-ddr.dtsi)
 
#define DDR_PCFGR_0 0x00010000
#define DDR_PCFGR_1 0x00010001
 
My Board (TF-A/stm32mp15-mx-dtsi)
 
#define DDR_PCFGR_0 0x00000000
#define DDR_PCFGR_1 0x00000000

Why are these registers different even though I have the same configuration?

    This topic has been closed for replies.
    Best answer by PatrickF

    HI @Gencay​ ,

    Although impact should be very limited (linked to read/write ordering inside the DDR controller), I confirm that the value in official delivery are the recommended one (See also AN5168).

    CubeMX generation will be aligned in future versions.

    To sum up, both DDR_PCFGR_0 and DDR_PCFGR_1 should be set to 0x00010000

    (I assume 0x00010001 in your post is a typo, if not please provide a link where you found this value)

    Regards.

    In order to give better visibility on the answered topics, please click on 'Select as Best' on the reply which solved your issue or answered your question. See also 'Best Answers'

    1 reply

    PatrickFAnswer
    Technical Moderator
    September 16, 2022

    HI @Gencay​ ,

    Although impact should be very limited (linked to read/write ordering inside the DDR controller), I confirm that the value in official delivery are the recommended one (See also AN5168).

    CubeMX generation will be aligned in future versions.

    To sum up, both DDR_PCFGR_0 and DDR_PCFGR_1 should be set to 0x00010000

    (I assume 0x00010001 in your post is a typo, if not please provide a link where you found this value)

    Regards.

    In order to give better visibility on the answered topics, please click on 'Select as Best' on the reply which solved your issue or answered your question. See also 'Best Answers'