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Visitor II
March 11, 2021
Question

Is there a way to use the B-LCDAD-HDMI adapter (bridge chip ADV7533) instead of the default panel DSI on the STM32MP157a-ev1 board?

  • March 11, 2021
  • 14 replies
  • 7264 views

Hi,

I tried to update the DTS to make use of the adapter but unfortunately without success. These are the change I made:

hdmi-out {
 compatible = "hdmi-connector";
 type = "a";
 
 port {
 hdmi_con: endpoint {
 remote-endpoint = <&adv7533_out>;
 };
 };
};
 
&dsi { 
 
 phy-dsi-supply = <&reg18>;
 
 #address-cells = <1>;
 #size-cells = <0>;
 status = "okay";
 
 ports {
 #address-cells = <1>;
 #size-cells = <0>;
 
 port@0 {
 reg = <0>;
 dsi_in: endpoint {
 remote-endpoint = <&ltdc_ep0_out>;	
 };
 };
 
 port@1 {
 reg = <1>;
 dsi_out: endpoint {
 remote-endpoint = <&adv7533_in>;
 };
 };
 };
};
 
&i2c2 {
 pinctrl-names = "default", "sleep";
 pinctrl-0 = <&i2c2_pins_a>;
 pinctrl-1 = <&i2c2_pins_sleep_a>;
 i2c-scl-rising-time-ns = <185>;
 i2c-scl-falling-time-ns = <20>;
 status = "okay";
 /delete-property/dmas;
 /delete-property/dma-names;
 
 hdmi-transmitter@3d {
 compatible = "adi,adv7533";
 reg = <0x3d>; // (3d = 7A>>1)
 
 a2vdd-supply = <&v1v8>;
 v3p3-supply = <&v3v3>;
 v1p2-supply = <&v1v8>;
 
 avdd-supply = <&v1v8>;
 dvdd-supply = <&v1v8>;
 pvdd-supply = <&v1v8>;
 dvdd-3v-supply = <&v3v3>;
 
 adi,dsi-lanes = <2>;
 adi,disable-timing-generator = <1>;
 
 status = "okay";
 
 ports {
 #address-cells = <1>;
 #size-cells = <0>;
 
 port@0 {
 reg = <0>;
 adv7533_in: endpoint {
 remote-endpoint = <&dsi_out>;
 };
 };
 
 port@1 {
 reg = <1>;
 adv7533_out: endpoint {
 remote-endpoint = <&hdmi_con>;
 };
 };
 };
 };

thanks in advance for your help.

Luca.

    This topic has been closed for replies.

    14 replies

    Explorer II
    March 11, 2021

    I just add the i2c2 traffic we get between the mp1 and the adv7533:

    write to 0x3D ack data: 0x00

    read to 0x3D ack data: 0x14

    write to 0x3D ack data: 0x16 0x20

    write to 0x3D ack data: 0x9A 0xE0

    write to 0x3D ack data: 0xBA 0x70

    write to 0x3D ack data: 0xDE 0x82

    write to 0x3D ack data: 0xE4 0x40

    write to 0x3D ack data: 0xE5 0x80

    write to 0x3D ack data: 0x44 0x00

    write to 0x3D ack data: 0x43 0x7E

    write to 0x3D ack data: 0x45 0x70

    write to 0x3C ack data: 0x15 0xD0

    write to 0x3C ack data: 0x17 0xD0

    write to 0x3C ack data: 0x24 0x20

    write to 0x3C ack data: 0x57 0x11

    write to 0x3C ack data: 0x05 0xC8

    write to 0x3D ack data: 0xE1 0x78

    write to 0x3C ack data: 0x03 0x0B

    write to 0x3C ack data: 0x27 0x0B

    Unfortunately, after this, the communication stops (and from my understanding also the AD7533 is put in sleep mode).

    Thank in advance for your help.

    Davide

    Graduate II
    March 11, 2021

    I don't have the linux stuff figured, but I have had assorted video modes running on the F769 via HDMI

    I can perhaps capture the ADV7533 interactions that work here.

    What's your notional display, resolution, timing, etc?

    Explorer II
    March 11, 2021

    Thank you for the reply!

    We hope to use this adaptor the same way the embed sil9022a works for the stm32mp157a-dk1 (but sourced from dsi, instead of ltdc parallel rgb). I think that timing and resolution is arbitrated by the linux drivers, as it scales with the connected hdmi display. At least this is my current understanding, but I can be wrong.

    If you could do the capture with ease, it can be of great help! With the mcu implementation you have to explicitly declare the hdmi display characteristics?

    Visitor II
    June 16, 2021

    Just curious if you managed to get B-LCDAD-HDMI adapter working with you board. I'm trying on my custom board but I can't get a stable test image from modetest. Everything is recognized but the ltdc timings don't seem to be setting. When I enable debug, i see

    drm:drm_mode_debug_printmodeline] Modeline "800x480": 68 33000 800 837 885 925 480 493 496 525 0x48 0xa

    but that info doesn't seem to set the ltdc timings properly.

    Visitor II
    August 6, 2021

    I managed to get B-LCDAD-HDMI adapter working with my custom board stm32mp157c board. I had to modify some source files in the linux kernel driver. The base version I'm using is 5.13.5-armv7-lpae-x13. I modified the file KERNEL/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c. In the routine dw_mipi_dsi_line_timer_config I changed the first timing parameter from htotal to hactive. For some reason the ADV7533 would not sync otherwise. This works for my system since I only have the ADV7533 on the dsi bus. If you are running other dsi peripherals you probably have to worry about virtual channels. Hope this helps.

    Regards

    Explorer II
    August 6, 2021

    Dear MKonz.1,

    thank you so much for sharing your workaroud. Your setup is the same as ours, no other dsi device other than the B-LCDAD-HDMI adapter.

    We will try your solution as soon as we come back to office and let you know!

    We had to stop testing with the hdmi adapter to focus on other development for out product.

    In pevious tests we didn’t get anything with modetest, we only were able to trace i2c comm from low level driver.

    In your board the INT line from the hdmi adapter is routed to the MPU? Maybe other than the software problem we had also an hardware issue.

    Many thanks again,

    Regards

    Visitor II
    August 18, 2021

    If modetest can't find your display you may have a problem with ADV7533 detect race condition. In the adv7511_drv.c file, I had to move the adv7533_attach_dsi(adv) call from adv7511_bridge_attach(...) routine to the end of adv7511_probe(..) routine. The kernel could then detect the ADV7533 and read the display EDID .

    in /sys/class/drm you should see your cardx-HDMI-x-x. In my case : card1-HDMI-A-1

    In the device tree, the interrupt is enabled:

    interrupt-parent = <&gpiof>;

    interrupts = <2 IRQ_TYPE_EDGE_FALLING>;

    as well as the powerdown..

    pd-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;

    Hope this helps.

    Regards

    Explorer II
    August 31, 2021

    Dear MKonz.1,

    And so it was, it really helped us a lot!

    The mod to the adv7511_drv.c file was key to finally get the kernel to detect ADV7533 and correctly read the display EDID. We also managed to add an IRQ line, even if we found that it doesn't change the behaviour of the driver, even without it, the kernel is able to detect an HDMI connector (plug-in and plug-out events) and EDID. Right now the are trying to find a less demanding screen as at boot we get:

    [ 18.513484] Time out check load galcore module expired
    [ 29.124419] Time out check galcore device expired
    [ 29.178322] Weston already configured on pixman
    [ 29.911176] [drm] Warning max phy mbps is used

    To also give some details, this is what we get we probe status "cat /sys/kernel/debug/dri/0/state":

    plane[30]: plane-0
     crtc=crtc-0
     fb=36
     allocated by = weston
     refcount=2
     format=XR24 little-endian (0x34325258)
     modifier=0x0
     size=1280x720
     layers:
     size[0]=1280x720
     pitch[0]=5120
     offset[0]=0
     obj[0]:
     name=0
     refcount=3
     start=00010000
     size=3686400
     imported=no
     crtc-pos=1280x720+0+0
     src-pos=1280.000000x720.000000+0.000000+0.000000
     rotation=1
     normalized-zpos=0
     color-encoding=ITU-R BT.601 YCbCr
     color-range=YCbCr limited range
     user_updates=0fps
    plane[33]: plane-1
     crtc=(null)
     fb=0
     crtc-pos=0x0+0+0
     src-pos=0.000000x0.000000+0.000000+0.000000
     rotation=1
     normalized-zpos=0
     color-encoding=ITU-R BT.601 YCbCr
     color-range=YCbCr limited range
     user_updates=0fps
    crtc[32]: crtc-0
     enable=1
     active=1
     planes_changed=1
     mode_changed=0
     active_changed=0
     connectors_changed=0
     color_mgmt_changed=0
     plane_mask=1
     connector_mask=1
     encoder_mask=1
     mode: 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
    connector[29]: HDMI-A-1
     crtc=crtc-0

    meminfo also report that the frame buffer has been allocated "cat /proc/meminfo | grep -I cma":

    CmaTotal: 131072 kB
    CmaFree: 105688 kB

    But no DMA/CMA has been allocated "cat /sys/kernel/debug/dma_buf/bufinfo":

    Dma-buf Objects:
    size flags mode count exp_name

    Finally, with DMS/KMS logs enabled "echo 0x02 > /sys/module/drm/parameters/debug" we get:

    // Only once, HDMI connector plug-in
    [ 946.608886] [drm:ltdc_crtc_mode_valid] clk rate target 148500000, available 148500000
    [ 946.608913] [drm:ltdc_crtc_mode_valid] clk rate target 147170000, available 118800000
    [ 946.608929] [drm:ltdc_crtc_mode_valid] clk rate target 148500000, available 148500000
    [ 946.608943] [drm:ltdc_crtc_mode_valid] clk rate target 108000000, available 99000000
    [ 946.608957] [drm:ltdc_crtc_mode_valid] clk rate target 108000000, available 99000000
    [ 946.608971] [drm:ltdc_crtc_mode_valid] clk rate target 136750000, available 118800000
    [ 946.608985] [drm:ltdc_crtc_mode_valid] clk rate target 88750000, available 84857143
    [ 946.608999] [drm:ltdc_crtc_mode_valid] clk rate target 119000000, available 118800000
    [ 946.609013] [drm:ltdc_crtc_mode_valid] clk rate target 74250000, available 74250000
    [ 946.609030] [drm:ltdc_crtc_mode_valid] clk rate target 40000000, available 39600000
    [ 946.609044] [drm:ltdc_crtc_mode_valid] clk rate target 31500000, available 31263158
    [ 946.609058] [drm:ltdc_crtc_mode_valid] clk rate target 31500000, available 31263158
    [ 946.609072] [drm:ltdc_crtc_mode_valid] clk rate target 30240000, available 29700000
    [ 946.609086] [drm:ltdc_crtc_mode_valid] clk rate target 25175000, available 24750000
    [ 946.609100] [drm:ltdc_crtc_mode_valid] clk rate target 28320000, available 28285715
    [ 946.609114] [drm:ltdc_crtc_mode_valid] clk rate target 135000000, available 118800000
    [ 946.609128] [drm:ltdc_crtc_mode_valid] clk rate target 78750000, available 74250000
    [ 946.609142] [drm:ltdc_crtc_mode_valid] clk rate target 65000000, available 59400000
    [ 946.609156] [drm:ltdc_crtc_mode_valid] clk rate target 49500000, available 49500000
    [ 946.609214] [drm:ltdc_crtc_mode_valid] clk rate target 25175000, available 24750000
    [ 946.609228] [drm:ltdc_crtc_mode_valid] clk rate target 27000000, available 27000000
    [ 946.609244] [drm:ltdc_crtc_mode_valid] clk rate target 27000000, available 27000000
    [ 946.609261] [drm:ltdc_crtc_mode_valid] clk rate target 148500000, available 148500000
    [ 946.609275] [drm:ltdc_crtc_mode_valid] clk rate target 27000000, available 27000000
    [ 946.609298] [drm:ltdc_crtc_mode_valid] clk rate target 27000000, available 27000000
    [ 946.609320] [drm:ltdc_crtc_mode_valid] clk rate target 74250000, available 74250000
    [ 946.609343] [drm:ltdc_crtc_mode_valid] clk rate target 148500000, available 148500000
    [ 946.609357] [drm:ltdc_crtc_mode_valid] clk rate target 74250000, available 74250000
    [ 946.609374] [drm:ltdc_crtc_mode_valid] clk rate target 74176000, available 66000000
    [ 946.609388] [drm:ltdc_crtc_mode_valid] clk rate target 25200000, available 24750000
    [ 946.609402] [drm:ltdc_crtc_mode_valid] clk rate target 27027000, available 27000000
    [ 946.609416] [drm:ltdc_crtc_mode_valid] clk rate target 27027000, available 27000000
    [ 946.609431] [drm:ltdc_crtc_mode_valid] clk rate target 148352000, available 118800000
    [ 946.638012] [drm:ltdc_plane_atomic_check] 
    [ 946.638033] [drm:ltdc_plane_atomic_check] 
    [ 946.647847] [drm:ltdc_plane_atomic_check] 
    [ 946.647878] [drm:ltdc_plane_atomic_check] plane:30 fb:37 (1280x720)@(0,0) -> (1280x720)@(0,0)
    [ 946.647889] [drm:ltdc_plane_atomic_check] 
    [ 946.648005] [drm:ltdc_plane_atomic_update] fb: phys 0xf7d00000
    [ 946.648022] [drm:ltdc_crtc_enable_vblank] 
    [ 947.001302] [drm:ltdc_plane_atomic_check] 
    [ 947.001335] [drm:ltdc_plane_atomic_check] plane:30 fb:37 (1280x720)@(0,0) -> (1280x720)@(0,0)
    [ 947.032752] [drm:ltdc_plane_atomic_check] 
    [ 947.032785] [drm:ltdc_plane_atomic_check] plane:30 fb:36 (1280x720)@(0,0) -> (1280x720)@(0,0)
    [ 947.032933] [drm:ltdc_plane_atomic_update] fb: phys 0xf7900000
    [ 952.109914] [drm:ltdc_crtc_disable_vblank] 
     
    // Repeating sequence
    [ 1006.637171] [drm:ltdc_crtc_enable_vblank] 
    [ 1006.650527] [drm:ltdc_plane_atomic_check] 
    [ 1006.650556] [drm:ltdc_plane_atomic_check] plane:30 fb:36 (1280x720)@(0,0) -> (1280x720)@(0,0)
    [ 1006.656782] [drm:ltdc_plane_atomic_check] 
    [ 1006.656813] [drm:ltdc_plane_atomic_check] plane:30 fb:37 (1280x720)@(0,0) -> (1280x720)@(0,0)
    [ 1006.656946] [drm:ltdc_plane_atomic_update] fb: phys 0xf7d00000
    [ 1011.709766] [drm:ltdc_crtc_disable_vblank] 
    [ 1066.635943] [drm:ltdc_crtc_enable_vblank] 
    [ 1066.651307] [drm:ltdc_plane_atomic_check] 
    [ 1066.651338] [drm:ltdc_plane_atomic_check] plane:30 fb:37 (1280x720)@(0,0) -> (1280x720)@(0,0)
    [ 1066.653817] [drm:ltdc_plane_atomic_check] 
    [ 1066.653846] [drm:ltdc_plane_atomic_check] plane:30 fb:36 (1280x720)@(0,0) -> (1280x720)@(0,0)
    [ 1066.653983] [drm:ltdc_plane_atomic_update] fb: phys 0xf7900000
    [ 1071.709705] [drm:ltdc_crtc_disable_vblank] 

    I don't get why it indicated so many valid modes, when "modetest -M STM" only gets 9 modes:

    Encoders:
    id crtc type possible crtcs possible clones
    28 32 DSI 0x00000001 0x00000000
     
    Connectors:
    id encoder status name size (mm) modes encoders
    29 28 connected HDMI-A-1 880x490 8 28
     modes:
     name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
     1280x720 60 1280 1390 1430 1650 720 725 730 750 74250 flags: phsync, pvsync; type: driver
     1280x720 60 1280 1390 1430 1650 720 725 730 750 74250 flags: phsync, pvsync; type: driver
     1280x720 50 1280 1720 1760 1980 720 725 730 750 74250 flags: phsync, pvsync; type: driver
     800x600 75 800 816 896 1056 600 601 604 625 49500 flags: phsync, pvsync; type: driver
     720x576 50 720 732 796 864 576 581 586 625 27000 flags: nhsync, nvsync; type: driver
     720x576 50 720 732 796 864 576 581 586 625 27000 flags: nhsync, nvsync; type: driver
     720x480 60 720 736 798 858 480 489 495 525 27000 flags: nhsync, nvsync; type: driver
     720x480 60 720 736 798 858 480 489 495 525 27000 flags: nhsync, nvsync; type: driver

    Unfortunately we are still getting no output, the monitor remains without input signal, as every time we try send a test pattern to the screen, as an example with "modetest -M stm -s 29@32:1280x720-50", we get:

    setting mode 1280x720-50Hz@XR24 on connectors 29
    crtc 32 failed to set mode: Permission denied

    Do you also think that the required pixel clock of our display is the key issue?

    Many thanks again,

    Regards

    Visitor II
    September 10, 2021

    I'm not sure. My display is 800x480 and is running correctly. Did you modify the dw-mipi-dsi.c routine I mentioned above to endure the horizontal active area is passed to the timing routine, not the horizontal total. I will try to a 1280 by 720 hdmi capable monitor and see what happens...

    Regards,

    Explorer II
    September 12, 2021

    Dear @MKonz.1​ 

    We've found an old RaspberryPi display with 1024x600 @ 30Hz and it worked ok with just the modification you've suggested.

    Event if it showed a consistent image, a good portion of the image was out of the display: the video output stream was still 1280x720 (like if it ignored the current display resolution and put out an "hardcoded" one).

    Maybe this is because last time we skipped the mod to the dw-mipi-dsi.c routine. Unfortunately we didn't really know what to modify specifically to specify an Horizontal Active Area, instead of the Horizontal Total... nor what is the Horizontal Active Area of our display.

    I assume Horizontal Active Area is the actual display pixel resolution (1024 in the case of the old RaspberryPi display), while the Horizontal Total is the pixel resolution of the ldc embedded controller (that is usually larger as generic controllers may be matched with generic display... in the case of the old RaspberryPi display this may be 1280). Am I right?

    Why the bigger 1280x720 isn't working is still unresolved from our side: if you can do the tests a monitor of yours it would be great!

    Thank you again

    Visitor II
    September 24, 2021

    Sorry, I've been wrapped up on on other problems on my development project. I will try to test the larger display next week. I have a feeling the 1280x720 resolution is too high for the 2 channel DSI without reducing colour depth and/or refresh.

    Explorer II
    September 29, 2021

    Dear @MKonz.1​ 

    Do not worry about the delay and many thanks for the update and help.

    I hope that you have solved the issue you had with your project, we'll wait for your test results.

    Meanwhile we managed to get a DK1 evaluation board (LTDC parallel interface routed to a Lattice Sil9022A), and in this case the HDMI port can handle our monitor at 1280x720 @ 60Hz. In fact it can even do more, adapting it's output size to the available monitor by reading the EDID at first plug-in event: so it can also drive the other 1024x600 @ 30Hz display. Unfortunately it won't adapt if a different monitor is plugged in after boot with another one of different resolution, but it is still something.

    We think that this is an indicator of two main issues: the first one, that you already pointed out, is that EV1 "ignore" display size as it was born with the idea to be used with only one DSI display (dw-mipi-dsi.c routine mod to hardcode horizontal active area); the other is maybe the inability of the 2 lanes DSI to support that pixel clock, but we need to further investigate.

    In the next day one of our colleague will take in hand this issue full-time, with a deep dive on DK1 modes of operations and what can be done to obtain the same results with EV1 and the HDMI adapter.

    Thank you again,

    Davide

    Explorer
    December 13, 2021

    Dear @MKonz.1​ 

    Sorry for some months of silence, I'm Marco a coworker of Davide in charge since last week of this part of the project.

    I made the change you suggested in file KERNEL/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c updating the mode->htotal parameter to mode->hdisplay in dw_mipi_dsi_line_timer_config routine (hdisplay is the name for hactive timing parameter in drm_display_mode structure), but nothing changes on our display (I'm testing with a 1024x600).

    I tried to do some changes using /etc/xdg/weston/weston.ini configuration file and I noticed that using B-LCDAD-HDMI adapter:

    • Changes done in [output] section of our HDMI-A-1 are completely ignored, e.g I tried to flip the display using transform=flipped
    • Changes done in [shell] section work, e.g I try to change panel position from bottom to top (panel-position=top)

    while both changes done with the display connected to a DK1's native HDMI port work without any troubles.

    As Davide wrote in his last post, DK1 handles our display without troubles using LTDC parallel interface routed to a Lattice Sil9022A through a DPI encoder, while our B-LCDAD-HDMI adapter use LTDC parallel interface routed to a ADV7533 through a DSI encoder.

    I tried to figure out where the different behaviour could take place and I think it could be on how ADV7533 communicates with the DSI: it seems communication is mislead or broken for some reasons and the system could only use a partial or a default (or hardcoded??) configuration which not completely fit our display. I don't know if there are some linux drivers to add or some other changes to do in the DSI driver.

    I hope you have some further suggestions or ideas for us

    Best Regards

    Marco.

    Technical Moderator
    December 13, 2021

    Hi,

    maybe this post could help: https://community.st.com/s/question/0D53W000018Ttf1SAC

    Regards.

    Explorer
    December 14, 2021

    Thank you @PatrickF​ for the immediate reply,

    I tried your solution (both kernel patch and device tree) but unfortunately doesn't solve our issue which seems to be linked to a wrong computation of horizontal back porch or to a misled communication of EDID informations.

    I add an image of my display hoping it could help to figure out the issue; if you have any other ideas or suggestions, they could be of help

    Best regards

    Marco.

    0693W00000HoXSGQA3.png

    ST Employee
    January 27, 2022

    The board MB1232 B-LCDAD-HDMI1 can be plugged on STM32MP157F-EV1 in place of the LCD panel.

    There are few patches sent for upstream Linux, but not merged yet, that allows the setup MB1232 on STM32MP157F-EV1 to work fine with latest OpenSTLinux 3.1.0 (kernel v5.10.61).

    These patches will soon be merged and become part of next OpenSTLinux deliveries.

    The rest of this post is about the setup MB1232 on STM32MP157F-EV1, but it can be easily generalized for other systems containing STM32MP15x plus ADV7533.

    This post covers the DSI to HDMI conversion only. Other features of ADV7533 (e.g. audio to HDMI) are not covered.

    With STM32MP157F-EV1 board powered off:

    • remove the camera module from STM32MP157F-EV1 (details below),
    • remove the LCD panel from STM32MP157F-EV1,
    • plug the MB1232 on the connector CN19 (DSI) of STM32MP157F-EV1, originally used by the LCD panel.

    NOTE: the connection MB1232 on STM32MP157F-EV1 is fine from electrical point of view, but the two boards cannot be mechanically locked/screwed together; the HDMI cable can easily force, move and disconnect the board MB1232. Try to use an highly flexible HDMI cable and pay close attention on the mechanical stability of the system.

    For the SW part, you need to patch and rebuild kernel and devicetree.

    You can download each of the patches below by opening the corresponding links and then clicking on the link "(raw)" beside the Message-ID.

    Use "git am ..." to apply each patch in the same order as listed below.

    1) https://lore.kernel.org/lkml/20211218182804.208906-1-antonio.borneo@foss.st.com/

    On STM32MP157F-EV1 the I2C address of the camera module conflicts with MB1232.

    ADV7533 allows reprogramming the I2C address, but such reprogramming should be done before Linux accesses the conflicting address.

    Unfortunately the probe of ADV7533 often happens after the probe of the camera, so the conflict can still create issues.

    The reprogramming of ADV7533 could be done in U-Boot, before Linux starts, but this is not covered in this current setup.

    As a quick workaround, for the time being, I suggest to keep the camera module unplugged.

    Without camera module, this patch is still relevant to avoid I2C address conflicts in the devicetree; the devicetree below requires this patch.

    2) https://lore.kernel.org/lkml/20211218215055.212421-1-antonio.borneo@foss.st.com/

    3) https://lore.kernel.org/lkml/20211218215055.212421-2-antonio.borneo@foss.st.com/

    4) https://lore.kernel.org/lkml/20211218215055.212421-3-antonio.borneo@foss.st.com/

    These patches instruct DSI to reject all the video modes that cannot be supported with the current clock.

    Without these patches the DSI never rejects a video mode, so the DRM framework can incorrectly choose a mode that cannot be displayed.

    HDMI panels are quite picky with the timings, so these patches are relevant for a correct setup of a DSI-to-HDMI bridge.

    ADV7533 does not accepts DSI burst mode, so STM32MP15x DSI must generate the exact pixel clock required by the HDMI panel.

    The STM32MP15x DSI has some limitation on the pixel clock values that can be generated.

    This script dumps all the DSI pixel clock values that are compatible with the STM32MP157F-EV1's on-board oscillator of 24 MHz:

    #!/bin/bash
    hse=24000000
    vcomin=1000000000
    vcomax=2000000000
    n_lanes=2
     
    # 24 bpp
    byte_per_pixel=3
     
    for i in {1..7}; do
     for n in {10..125}; do
     vco=$(($hse*2*$n/$i))
     if [ $vco -lt $vcomin -o $vco -gt $vcomax ]; then
     continue
     fi
     for o in 1 2 4 8; do
     hs_clk=$(($hse*$n/($i*$o)))
     echo $(($hs_clk*$n_lanes/(8*$byte_per_pixel)))
     done
     done
    done | sort -nu

    NOTE: If you need to support a specific pixel clock not listed by the script, you can consider replacing the 24 MHz main oscillator on the board (HSE clock).

    You can find information about the oscillator's frequencies allowed by the bootrom of STM32MP1 in

    https://wiki.st.com/stm32mpu/wiki/STM32MP15_ROM_code_overview#USB_Boot

    If you change oscillator, you should align the clock configuration in TF-A devicetree

    https://wiki.st.com/stm32mpu/wiki/Clock_device_tree_configuration_-_Bootloader_specific

    Modify the variable "hse" in the script above to dump the pixel frequencies for different oscillators.

    With the patches above applied, add the change in attachment for the kernel's devicetree to disable the (removed) STM32MP157F-EV1 panel and enable the MB1232.

    ST Employee
    February 20, 2022

    I have just edited the script in my previous message.

    The former script was dumping only the HS clock on the DSI output, not the pixel clock.

    Sorry for the mistake.

    Explorer
    November 19, 2024

    Hello
    I'm trying to use B-LCDAD-HDMI adapter on kernel v6.1-stm32mp-r2
    Many of above information are very useful but of course some are outdated
    First strange thing is in ADV7533 driver.
    In function adv7533_mode_fixup
    https://github.com/STMicroelectronics/linux/blob/4c4175804a542f40c50d091cc694bb0b186728a0/drivers/gpu/drm/bridge/adv7511/adv7533.c#L123C6-L123C25
    dsi lines are changed to 3 or 4.
    But as I know in STM32MP157 we have only 2 lines.
    I've commented it out and return true every time. I suppose this is not best solution, but I don't know what can be better now.

    Finally after command
    # modetest -M stm -s 32:800x600
    I don't see test screen. Below is detailed log. I suppose important is last 10-20 lines.

     

    # modetest -M stm
    Encoders:
    id crtc type possible crtcs possible clones
    31 0 DSI 0x00000001 0x00000001

    Connectors:
    id encoder status name size (mm) modes encoders
    32 0 connected HDMI-A-1 600x340 1 31
    modes:
    index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
    #0 800x600 72.19 800 856 976 1040 600 637 643 666 50000 flags: phsync, pvsync; type: driver
    props:
    1 EDID:
    flags: immutable blob
    blobs:

    value:
    00ffffffffffff004a8b32bc01010101
    091a0103803c22783eee91a3544c9926
    0f5054bfef80d1c0d1e8d1fc95009040
    8180814081c0201c56a050001630582c
    250055502100001e000000fc0052544b
    2046484420484452200a000000ff0064
    656d6f7365742d310a203020000000fd
    00324b545413010a202020202020017e
    020332f24f04051013141f2021222748
    494a4b4ce200d5e305c00023097f0783
    01000067030c001000383ce606050162
    6200201c56a050002830582c25005550
    2100001e011d8018711c1620582c2500
    55502100009e00000000000000000000
    00000000000000000000000000000000
    000000000000000000000000000000fb
    2 DPMS:
    flags: enum
    enums: On=0 Standby=1 Suspend=2 Off=3
    value: 0
    5 link-status:
    flags: enum
    enums: Good=0 Bad=1
    value: 0
    6 non-desktop:
    flags: immutable range
    values: 0 1
    value: 0
    4 TILE:
    flags: immutable blob
    blobs:

    value:
    33 dithering:
    flags: enum
    enums: Off=0 On=1
    value: 0

    CRTCs:
    id fb pos size
    38 0 (0,0) (0x0)
    #0 nan 0 0 0 0 0 0 0 0 0 flags: ; type:
    props:
    24 VRR_ENABLED:
    flags: range
    values: 0 1
    value: 0
    28 GAMMA_LUT:
    flags: blob
    blobs:

    value:
    29 GAMMA_LUT_SIZE:
    flags: immutable range
    values: 0 4294967295
    value: 256

    Planes:
    id crtc fb CRTC x,y x,y gamma size possible crtcs
    34 0 0 0,0 0,0 0 0x00000001
    formats: AR24 XR24 RG24 RG16 AR15 XR15 AR12 XR12 C8
    props:
    8 type:
    flags: immutable enum
    enums: Overlay=0 Primary=1 Cursor=2
    value: 1
    30 IN_FORMATS:
    flags: immutable blob
    blobs:

    value:
    01000000000000000900000018000000
    01000000400000004152323458523234
    52473234524731364152313558523135
    41523132585231324338202000000000
    ff010000000000000000000000000000
    0000000000000000
    in_formats blob decoded:
    AR24: LINEAR(0x0)
    XR24: LINEAR(0x0)
    RG24: LINEAR(0x0)
    RG16: LINEAR(0x0)
    AR15: LINEAR(0x0)
    XR15: LINEAR(0x0)
    AR12: LINEAR(0x0)
    XR12: LINEAR(0x0)
    C8: LINEAR(0x0)
    36 alpha:
    flags: range
    values: 0 65535
    value: 65535
    37 zpos:
    flags: immutable range
    values: 0 0
    value: 0
    39 0 0 0,0 0,0 0 0x00000001
    formats: AR24 RG24 RG16 AR15 AR12 C8
    props:
    8 type:
    flags: immutable enum
    enums: Overlay=0 Primary=1 Cursor=2
    value: 0
    30 IN_FORMATS:
    flags: immutable blob
    blobs:

    value:
    01000000000000000600000018000000
    01000000300000004152323452473234
    52473136415231354152313243382020
    3f000000000000000000000000000000
    0000000000000000
    in_formats blob decoded:
    AR24: LINEAR(0x0)
    RG24: LINEAR(0x0)
    RG16: LINEAR(0x0)
    AR15: LINEAR(0x0)
    AR12: LINEAR(0x0)
    C8: LINEAR(0x0)
    41 alpha:
    flags: range
    values: 0 65535
    value: 65535
    42 zpos:
    flags: immutable range
    values: 1 1
    value: 1

    Frame buffers:
    id size pitch

    # modetest -M stm -s 32:800x600
    setting mode 800x600-72.19Hz on connectors 32, crtc 38

    # dmesg
    [ 221.921975] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:32:HDMI-A-1]
    [ 222.039326] [drm:update_display_info] Supported Monitor Refresh rate range is 50 Hz - 75 Hz
    [ 222.039397] [drm:drm_parse_cea_ext] CEA VCDB 0xd5
    [ 222.039428] [drm:drm_parse_cea_ext] HDMI: DVI dual 0, max TMDS clock 300000 kHz
    [ 222.039501] [drm:update_display_info] Supported Monitor Refresh rate range is 50 Hz - 75 Hz
    [ 222.039537] [drm:drm_parse_cea_ext] CEA VCDB 0xd5
    [ 222.039563] [drm:drm_parse_cea_ext] HDMI: DVI dual 0, max TMDS clock 300000 kHz
    [ 222.039596] [drm:drm_edid_to_eld] ELD monitor RTK FHD HDR
    [ 222.039626] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
    [ 222.039659] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
    [ 222.042828] [drm:ltdc_encoder_mode_valid] clk rate target 50000000, available 50000000
    [ 222.042986] [drm:dw_mipi_dsi_stm_resume]
    [ 222.043053] [drm:dw_mipi_dsi_clk_recalc_rate]
    [ 222.043092] [drm:dw_mipi_dsi_stm_suspend]
    [ 222.043339] [drm:ltdc_encoder_mode_valid] clk rate target 72000000, available 68181819
    [ 222.043422] [drm:dw_mipi_dsi_stm_resume]
    [ 222.043469] [drm:dw_mipi_dsi_clk_recalc_rate]
    [ 222.043503] [drm:dw_mipi_dsi_stm_suspend]
    [ 222.043579] [drm:ltdc_encoder_mode_valid] clk rate target 72000000, available 68181819
    [ 222.043623] [drm:ltdc_encoder_mode_valid] clk rate target 88750000, available 83333334
    [ 222.043659] [drm:ltdc_encoder_mode_valid] clk rate target 101000000, available 93750000
    [ 222.043696] [drm:ltdc_encoder_mode_valid] clk rate target 108000000, available 107142858
    [ 222.043732] [drm:ltdc_encoder_mode_valid] clk rate target 108000000, available 107142858
    [ 222.043768] [drm:ltdc_encoder_mode_valid] clk rate target 74250000, available 68181819
    [ 222.043803] [drm:ltdc_encoder_mode_valid] clk rate target 40000000, available 39473685
    [ 222.043838] [drm:ltdc_encoder_mode_valid] clk rate target 36000000, available 35714286
    [ 222.043873] [drm:ltdc_encoder_mode_valid] clk rate target 31500000, available 31250000
    [ 222.043907] [drm:ltdc_encoder_mode_valid] clk rate target 31500000, available 31250000
    [ 222.043942] [drm:ltdc_encoder_mode_valid] clk rate target 30240000, available 30000000
    [ 222.043977] [drm:ltdc_encoder_mode_valid] clk rate target 25175000, available 25000000
    [ 222.044011] [drm:ltdc_encoder_mode_valid] clk rate target 28320000, available 27777778
    [ 222.044046] [drm:ltdc_encoder_mode_valid] clk rate target 135000000, available 125000000
    [ 222.044082] [drm:ltdc_encoder_mode_valid] clk rate target 78750000, available 75000000
    [ 222.044116] [drm:ltdc_encoder_mode_valid] clk rate target 75000000, available 75000000
    [ 222.044172] [drm:dw_mipi_dsi_stm_resume]
    [ 222.044215] [drm:dw_mipi_dsi_clk_recalc_rate]
    [ 222.044247] [drm:dw_mipi_dsi_stm_suspend]
    [ 222.044316] [drm:ltdc_encoder_mode_valid] clk rate target 65000000, available 62500000
    [ 222.044356] [drm:ltdc_encoder_mode_valid] clk rate target 57284000, available 53571429
    [ 222.044391] [drm:ltdc_encoder_mode_valid] clk rate target 49500000, available 46875000
    [ 222.044426] [drm:ltdc_encoder_mode_valid] clk rate target 108000000, available 107142858
    [ 222.044462] [drm:ltdc_encoder_mode_valid] clk rate target 74250000, available 68181819
    [ 222.044498] [drm:ltdc_encoder_mode_valid] clk rate target 148500000, available 125000000
    [ 222.044533] [drm:ltdc_encoder_mode_valid] clk rate target 74250000, available 68181819
    [ 222.044568] [drm:ltdc_encoder_mode_valid] clk rate target 148500000, available 125000000
    [ 222.044604] [drm:ltdc_encoder_mode_valid] clk rate target 74250000, available 68181819
    [ 222.044639] [drm:ltdc_encoder_mode_valid] clk rate target 74250000, available 68181819
    [ 222.044673] [drm:ltdc_encoder_mode_valid] clk rate target 74250000, available 68181819
    [ 222.044708] [drm:ltdc_encoder_mode_valid] clk rate target 74250000, available 68181819
    [ 222.044743] [drm:ltdc_encoder_mode_valid] clk rate target 74250000, available 68181819
    [ 222.044777] [drm:ltdc_encoder_mode_valid] clk rate target 74250000, available 68181819
    [ 222.044812] [drm:ltdc_encoder_mode_valid] clk rate target 148500000, available 125000000
    [ 222.044847] [drm:ltdc_encoder_mode_valid] clk rate target 148500000, available 125000000
    [ 222.044883] [drm:ltdc_encoder_mode_valid] clk rate target 74176000, available 68181819
    [ 222.044918] [drm:ltdc_encoder_mode_valid] clk rate target 25200000, available 25000000
    [ 222.044952] [drm:ltdc_encoder_mode_valid] clk rate target 148352000, available 125000000
    [ 222.044988] [drm:ltdc_encoder_mode_valid] clk rate target 74176000, available 68181819
    [ 222.045023] [drm:ltdc_encoder_mode_valid] clk rate target 74176000, available 68181819
    [ 222.045058] [drm:ltdc_encoder_mode_valid] clk rate target 74176000, available 68181819
    [ 222.045092] [drm:ltdc_encoder_mode_valid] clk rate target 74176000, available 68181819
    [ 222.045127] [drm:ltdc_encoder_mode_valid] clk rate target 148352000, available 125000000
    [ 222.045161] [drm:drm_mode_debug_printmodeline] Modeline "1366x768": 60 72000 1366 1454 1498 1526 768 770 775 790 0x48 0x5
    [ 222.045204] [drm:drm_mode_prune_invalid] Not using 1366x768 mode: CLOCK_HIGH
    [ 222.045232] [drm:drm_mode_debug_printmodeline] Modeline "1366x768": 58 72000 1366 1454 1498 1526 768 770 775 808 0x40 0x5
    [ 222.045271] [drm:drm_mode_prune_invalid] Not using 1366x768 mode: CLOCK_RANGE
    [ 222.045296] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
    [ 222.045334] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE
    [ 222.045359] [drm:drm_mode_debug_printmodeline] Modeline "1440x900": 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
    [ 222.045397] [drm:drm_mode_prune_invalid] Not using 1440x900 mode: CLOCK_RANGE
    [ 222.045422] [drm:drm_mode_debug_printmodeline] Modeline "1400x1050": 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
    [ 222.045460] [drm:drm_mode_prune_invalid] Not using 1400x1050 mode: CLOCK_HIGH
    [ 222.045485] [drm:drm_mode_debug_printmodeline] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
    [ 222.045523] [drm:drm_mode_prune_invalid] Not using 1280x1024 mode: CLOCK_HIGH
    [ 222.045547] [drm:drm_mode_debug_printmodeline] Modeline "1280x960": 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
    [ 222.045585] [drm:drm_mode_prune_invalid] Not using 1280x960 mode: CLOCK_HIGH
    [ 222.045610] [drm:drm_mode_debug_printmodeline] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
    [ 222.045648] [drm:drm_mode_prune_invalid] Not using 1280x720 mode: CLOCK_RANGE
    [ 222.045672] [drm:drm_mode_debug_printmodeline] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
    [ 222.045710] [drm:drm_mode_prune_invalid] Not using 800x600 mode: CLOCK_RANGE
    [ 222.045735] [drm:drm_mode_debug_printmodeline] Modeline "800x600": 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
    [ 222.045773] [drm:drm_mode_prune_invalid] Not using 800x600 mode: CLOCK_RANGE
    [ 222.045797] [drm:drm_mode_debug_printmodeline] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
    [ 222.045835] [drm:drm_mode_prune_invalid] Not using 640x480 mode: CLOCK_RANGE
    [ 222.045860] [drm:drm_mode_debug_printmodeline] Modeline "640x480": 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
    [ 222.045898] [drm:drm_mode_prune_invalid] Not using 640x480 mode: CLOCK_RANGE
    [ 222.045922] [drm:drm_mode_debug_printmodeline] Modeline "640x480": 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
    [ 222.045960] [drm:drm_mode_prune_invalid] Not using 640x480 mode: CLOCK_RANGE
    [ 222.045984] [drm:drm_mode_debug_printmodeline] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
    [ 222.046022] [drm:drm_mode_prune_invalid] Not using 640x480 mode: CLOCK_RANGE
    [ 222.046047] [drm:drm_mode_debug_printmodeline] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
    [ 222.046085] [drm:drm_mode_prune_invalid] Not using 720x400 mode: CLOCK_RANGE
    [ 222.046109] [drm:drm_mode_debug_printmodeline] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
    [ 222.046147] [drm:drm_mode_prune_invalid] Not using 1280x1024 mode: CLOCK_HIGH
    [ 222.046172] [drm:drm_mode_debug_printmodeline] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
    [ 222.046210] [drm:drm_mode_prune_invalid] Not using 1024x768 mode: CLOCK_RANGE
    [ 222.046235] [drm:drm_mode_debug_printmodeline] Modeline "1024x768": 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
    [ 222.046273] [drm:drm_mode_prune_invalid] Not using 1024x768 mode: CLOCK_HIGH
    [ 222.046298] [drm:drm_mode_debug_printmodeline] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
    [ 222.046336] [drm:drm_mode_prune_invalid] Not using 1024x768 mode: CLOCK_RANGE
    [ 222.046360] [drm:drm_mode_debug_printmodeline] Modeline "832x624": 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
    [ 222.046399] [drm:drm_mode_prune_invalid] Not using 832x624 mode: CLOCK_RANGE
    [ 222.046423] [drm:drm_mode_debug_printmodeline] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
    [ 222.046461] [drm:drm_mode_prune_invalid] Not using 800x600 mode: CLOCK_RANGE
    [ 222.046486] [drm:drm_mode_debug_printmodeline] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
    [ 222.046524] [drm:drm_mode_prune_invalid] Not using 1152x864 mode: CLOCK_HIGH
    [ 222.046549] [drm:drm_mode_debug_printmodeline] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
    [ 222.046587] [drm:drm_mode_prune_invalid] Not using 1280x720 mode: CLOCK_RANGE
    [ 222.046611] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
    [ 222.046650] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE
    [ 222.046674] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
    [ 222.046713] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_HIGH
    [ 222.046737] [drm:drm_mode_debug_printmodeline] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
    [ 222.046775] [drm:drm_mode_prune_invalid] Not using 1280x720 mode: CLOCK_RANGE
    [ 222.046800] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
    [ 222.046838] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE
    [ 222.046863] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
    [ 222.046901] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_HIGH
    [ 222.046926] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
    [ 222.046963] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_RANGE
    [ 222.046988] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
    [ 222.047026] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_RANGE
    [ 222.047051] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
    [ 222.047089] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_RANGE
    [ 222.047114] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080i": 50 72000 1920 1952 2120 2304 1080 1126 1136 1250 0x40 0x19
    [ 222.047152] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE
    [ 222.047178] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
    [ 222.047217] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_RANGE
    [ 222.047242] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
    [ 222.047281] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_RANGE
    [ 222.047305] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
    [ 222.047343] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_RANGE
    [ 222.047367] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
    [ 222.047405] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_HIGH
    [ 222.047429] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
    [ 222.047467] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_HIGH
    [ 222.047491] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
    [ 222.047530] [drm:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE
    [ 222.047554] [drm:drm_mode_debug_printmodeline] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
    [ 222.047592] [drm:drm_mode_prune_invalid] Not using 1280x720 mode: CLOCK_RANGE
    [ 222.047616] [drm:drm_mode_debug_printmodeline] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
    [ 222.047654] [drm:drm_mode_prune_invalid] Not using 640x480 mode: CLOCK_RANGE
    [ 222.047678] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
    [ 222.047715] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_HIGH
    [ 222.047739] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
    [ 222.047777] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_RANGE
    [ 222.047801] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
    [ 222.047839] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_RANGE
    [ 222.047863] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
    [ 222.047901] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_RANGE
    [ 222.047925] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
    [ 222.047963] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_RANGE
    [ 222.047987] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
    [ 222.048025] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_HIGH
    [ 222.048052] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:32:HDMI-A-1] probed modes :
    [ 222.048087] [drm:drm_mode_debug_printmodeline] Modeline "800x600": 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
    [ 222.062680] stm32-display 5a001000.display-controller: [drm:drm_mode_addfb2] [FB:43]
    [ 222.062922] [drm:drm_mode_setcrtc] [CRTC:38:crtc-0]
    [ 222.062994] [drm:drm_mode_setcrtc] [CONNECTOR:32:HDMI-A-1]
    [ 222.063122] [drm:ltdc_encoder_mode_valid] clk rate target 50000000, available 50000000
    [ 222.063238] [drm:dw_mipi_dsi_stm_resume]
    [ 222.063310] [drm:dw_mipi_dsi_clk_recalc_rate]
    [ 222.063352] [drm:dw_mipi_dsi_stm_suspend]
    [ 222.068368] [drm:ltdc_encoder_mode_fixup] requested clock 50000kHz, adjusted clock 50000kHz
    [ 222.068428] [drm:ltdc_plane_atomic_check]
    [ 222.068496] [drm:ltdc_crtc_mode_set_nofb]
    [ 222.068532] [drm:drv_runtime_suspend]
    [ 222.068559] [drm:ltdc_suspend]
    [ 222.068598] [drm:drv_runtime_resume]
    [ 222.068625] [drm:ltdc_resume]
    [ 222.068650] [drm:ltdc_crtc_mode_set_nofb] CRTC:38 mode:800x600
    [ 222.068673] [drm:ltdc_crtc_mode_set_nofb] Video mode: 800x600
    [ 222.068691] [drm:ltdc_crtc_mode_set_nofb] hfp 56 hbp 64 hsl 120 vfp 37 vbp 23 vsl 6
    [ 222.068736] [drm:dw_mipi_dsi_stm_resume]
    [ 222.068819] [drm:dw_mipi_dsi_clk_recalc_rate]
    [ 222.068895] [drm:dw_mipi_dsi_clk_round_rate]
    [ 222.068930] [drm:dw_mipi_dsi_clk_round_rate]
    [ 222.068963] [drm:dw_mipi_dsi_clk_set_rate]
    [ 222.068994] [drm:dw_mipi_dsi_clk_recalc_rate]
    [ 222.069024] [drm:dw_mipi_dsi_clk_enable]
    [ 222.071056] [drm:dw_mipi_dsi_clk_disable]
    [ 222.071087] [drm:dw_mipi_dsi_get_lane_mbps] pll_in 24000kHz pll_out 600000kHz lane_mbps 600MHz
    [ 222.071136] [drm:dw_mipi_dsi_clk_enable]
    [ 222.084039] [drm:dw_mipi_dsi_dphy_enable] failed to wait phy lock state
    [ 222.131892] [drm:dw_mipi_dsi_phy_power_on]
    [ 222.131969] [drm:ltdc_plane_atomic_update] plane:34 fb:43 src: 800x600+0+0 -> crtc: 800x600+0+0
    [ 222.132028] [drm:ltdc_plane_atomic_update] fb: phys 0xda100000
    [ 222.132076] [drm:ltdc_crtc_atomic_enable]
    [ 222.161212] [drm:ltdc_crtc_enable_vblank]
    [ 227.191822] [drm:ltdc_crtc_disable_vblank]
    [ 228.058990] stm32-display 5a001000.display-controller: [drm:drm_mode_rmfb_work_fn] Removing [FB:43] from all active usage due to RMFB ioctl
    [ 228.059080] stm32-display 5a001000.display-controller: [drm:atomic_remove_fb] Disabling [PLANE:34:plane-0] because [FB:43] is removed
    [ 228.059151] [drm:ltdc_plane_atomic_check]
    [ 228.059239] [drm:ltdc_plane_atomic_disable] CRTC:38 plane:34
    [ 228.059273] [drm:ltdc_crtc_enable_vblank]

     

     

    best regards