IWDG1 bit is not set in RCC status register

[Srikanth1]

Hello

     We are using STM32MP157A processor in our custom board. 

     Now we are implemented IWDG1 in Cortex A7 processor. The IWDG1 bit is not going to set after reset the processor with Watchdog timeout.

we checked in following registers

• RCC BOOTROM reset status clear register (RCC_BR_RSTSCLRR),
• RCC MCU reset status clear register (RCC_MC_RSTSCLRR),
• RCC MPU reset status clear register (RCC_MP_RSTSCLRR) and
• RCC MPU reset status set register (RCC_MP_RSTSSETR).

    Getting same value in these registers while power on reset and IWDG1 reset.

May be what was the issue, any one help me in this regards.

regards

srikanth

[PatrickF]

Hi,

you don't give much information on the setup.

If you use STPMIC1, when NRST toggling is detected (i.e. Watchdog or SW reset request), there is a complete power cycle done (unless SW program STPMIC1 at run time to behave differently).

So, in that case, you will see a POR reset reason.

In our starter package SW, we reprogram STPMIC in OpTEE to avoid VDD power cycle, thus allowing to get correct reset reason in the registers (if reset does not occur during boot, before OpTEE is started).

 

Regards.

 

[Srikanth1]

Thank you for reply.

   <In our starter package SW, we reprogram STPMIC in OpTEE to avoid VDD power cycle>

     I am also using STPMIC1, how can I program these bits in my STPMIC1 can you help in these regards

   

 

[PatrickF]

Hi,

please refer to STPMIC1 datasheet mask_reset settings.

 

bit = 1 mean the NRST activation will not have action on this supply (i.e. no power cycle)

 

Regards.