ksz8041 bring up

[MWoło.2]

It seems that I have a problem with DMA, but I'm not sure. Would you please take a look at the below screen

Dts looks

I intend to achieve MII with self-generated quartz.

Unfortunately, I'm stuck on this "Failed to reset the DMA".

[PatrickF]

Hi,

the message 'failed to reset the DMA' come usually from a missing clock on the GMAC (usually a clock from the PHY) which avoid the driver to correctly initialize the GMAC (ETH IP).

Please check the RefMan RCC "Clock distribution for Ethernet (ETH)".

See also https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration

By "self-generated quartz", could you confirm that this indicates there is a 25MHz Crystal on the PHY ?

Btw, if your PHY also support RMII, we encourage to use this interface.

Regards.

[MWoło.2]

Hi Patrick,

I have self-generated quartz. I check using an oscilloscope and sine waveform exist on pin XI/REFCLK equals 25MHz.

Regarding RMII I need to use 50MHz? I decided to use MII, but if for some reason it is a problem I can change it in the next revision. If RMII can work on 25MHz I need to change just one resistor on PCB.

Below parts of my schematic

and

Connections generated from CubeMX.

In my current project, ETH_CLK is used as SPI1_MOSI and as ENET1-RX-CLK

Unfortunately on

Ethernet device tree configuration - stm32mpu

there is no MII configuration.

[PatrickF]

Hi,

please try to remove the

st,ext-phyclk;

If it does not work after this change, please check the SYSCFG_PMCSETR register, by using either:

• uBoot: md 0x50020004
• Linux: devmem2 0x50020004 W (need to install devmem2 on the target which might be an issue without network)

field ETH_SEL should be 0b000

field ETH_SELMII should be 1

field ETH_REF_CLK_SEL should be 0

Regards

[MWoło.2]

Hi,

The result has been taken after stopped U-Boot execution. Of course, remove st,ext-phyclk; from U-Boot dts and Kernel dts.

And similar in the Kernel

How to set this bit. Do I miss something in dts, or maybe this is still a hardware issue?

[PatrickF]

Hi,

according to uBoot dump, seems the value at 0x50020004 is 0x0020000, which could be explained by st,ext-phyclk;

Please check you are really using the expected DT.

Maybe share complete DT and uBoot + Linux log files.

please check you have st,syscon = <&syscfg 0x4>;

It should be present by default in ethernet0 node from the included stm32mp151.dtsi file during DT compilation

For kernel dump, maybe need to enable the SYSCFG bus clock before reading which could explain the read of 0.

please try:

devmem2 0x50000A10 W 0x00000800
devmem2 0x50020004 W

Regards,

[MWoło.2]

Hi Patrick,

sorry for the delay.

In the attachment, boot logs.

Unfortunately, nothing helps.

[MWoło.2]

I also add my dts files. IMHO there could be some dts issue or a driver. I used the latest MMDV - "openstlinux-5.10-dunfell-mp1-21-03-31".

[MWoło.2]

FIles

[MWoło.2]

In dts it could be a bit mesh I try to check many options, parameters.

[OlivierK]

Hi MWoło.2 (Community Member)

What is the value of the SYSCFG_PMCSETR register one you've booted up the kernel?

> devmem2 0x50000A10 W 0x00000800

> devmem2 0x50020004 W

Regards