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Graduate II
May 13, 2024
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Memory equalization - How are the traces measured?

  • May 13, 2024
  • 2 replies
  • 3614 views

I downloaded the STM32MP151AAC3 example model (.zip file) that routes traces to the DDR3L memory

STM32MP151A - MPU with Arm Cortex-A7 650 MHz, Arm Cortex-M4 real-time coprocessor, TFT display - STMicroelectronics

 

Then I measured DDR_Q1 to DDR_7, DQM0, DQS0_P and DQS0_N and filled the Excel table that is included inside the downloaded .zip file.

Here is the result:

I have been using Altium CircuitMaker (very similar to Altium Designer).

Skärmbild 2024-05-13 231908.png

I measured by first pressing CTRL+H and then mark one part of the track and then I press this button.

Skärmbild 2024-05-13 232102.png

But when I look at the Excel spred sheet that ST have made, they show me these numbers.

My question is: What are ST doing to getting the length of DQ0, DQ1, DQ5 and DQ6 ? It seems that they are the only ones that differs. Others seems to be similar. 

If they are changed in the model, but not in the Excel spred sheet, which values should I follow? The values made by ST, or the hard ware example model made by ST?

Skärmbild 2024-05-13 232309.png

 

The reason why I'm asking this question is becuse the minimal clearance in the BGA for the DDR3L tracks, is 0.08mm. I need to re-route some tracks to increase the minimal electrical clearance.

    This topic has been closed for replies.
    Best answer by PatrickF

    Hi @DMårt 

    that's a question to Altium support I guess.

    As you might understand, we did not offer PCB review for community users.

    Regards.

    2 replies

    Technical Moderator
    May 17, 2024

    HI @DMårt 

    I'm not expert, but checking with Altium Designer, I see length in excel is very close to the value from the PCB file. So, no issue there

    PatrickF_3-1715938946160.png

     

    PatrickF_4-1715938979640.png

     

    DQ1 details

    PatrickF_5-1715939227886.png

     

    Regards.

     

     

    DMårtAuthor
    Graduate II
    May 20, 2024

    @PatrickF 

    Thank you!

    I have re-routed the upper layer traces and it seems very promising.

    Skärmbild 2024-05-21 011107.png

     

    But for the lower traces, I have a question about the lengths: Should the lengths of the pull-up traces count with the lenghts of the signal traces?

    Or is the only length between MCU pad and DDR pad, including PCB thickness times 2 (it's 2 vias)?

    Skärmbild 2024-05-21 011302.png

     

    Technical Moderator
    May 21, 2024

    Hi @DMårt 

    track length put in excel sheet should be calculated from MP1 to DDR (ball to ball), excluding the termination resistor track (which should be as short as possible, no length equalization).

    Obviously, termination resistor track should be 'after' the MP1 to DDR track (no 'T' routing which break impedance and signal integrity). What I see above seems not good.

    Quick explanation: Lenght equalization is for MP1/DDR timing propagation (i.e. signals must be sampled at right time). Termination resistors are for signal integrity (reflections).

    Notice that termination resistors are optional when using a single DDR3L x 16 bits (Although we have it on our reference boards, many customers does not have it without any issues)

    Regards.

    DMårtAuthor
    Graduate II
    May 23, 2024

    @PatrickF 

    Hi!

    I have a question about measurement. Can you check if I have done right? 

    If I share my Altium project with you so you can view the length of the DDR conductors and compare it with Altium Designer. I have Altium CircuitMaker. Is that OK?

     

    Because when I measure the initial example from ST, the DDR routings seems not to be correct according to the lengths.

    I had to re-route every track of the example from ST.

     

    PatrickFAnswer
    Technical Moderator
    May 23, 2024

    Hi @DMårt 

    that's a question to Altium support I guess.

    As you might understand, we did not offer PCB review for community users.

    Regards.

    DMårtAuthor
    Graduate II
    May 26, 2024

    @PatrickF 

    I understand.

    I just want to tell ST that the initial example has not correct lengths for their DDR routings.

    They have inclueded the short stub into the calculations.