Multiples Content Coherence Issue between STM32CubeMP1 and STM32MP15x Reference Manual

[Mohammed-Ismail Ben Salah]

Hello,

We are currently building a product using a STM32MP157 processor and are facing multiples discrepancies between the Reference Manual and the STM32MP1 Cube Package.

STM32CubeMP1 register memory map :

https://github.com/STMicroelectronics/STM32CubeMP1/blob/master/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h

As example we've taken the TAMP peripheral register map and noticed that the C structure has 128 BKP register but the documentation states only 32.

Another one is the the GPIO structure where the documentation states 1 reserved word betwen BRR and SECR but in the CMSIS file there's 2 word reserved. In the case of the GPIO structure the size goes up to 0x404 bytes (which is out of bounds)

It's quite painful to reverse engineer each time and check if the size of the structure is somehow fitting into the allocated space given in the boundary memory map.

Usually we consider the prototypes files are less error prone than the documentation,however in this case we experienced problems on both sides.

Therefore we would be happy to know if there's a corrected version of the device prototype file ?

Best Regards and thanks in advance for your answers,

Ismail Ben Salah

[Olivier GALLIEN]

Hi @Mohammed-Ismail Ben Salah​ 

Thanks for your message and for pointing out all these mismatch.

Since A7 bare metal support is not in the ecosystem offer for MP1, the CA7 header file suffer a very low validation effort.

We are fixing issues reported by customer but keep in mind that you should rely on Reference Manual first.

BR,

Olivier