Passive tamper detection at PC1 pin in STM32MP151

[jandriea]

I am using 2 passive tamper detection in my board that is routed to PC1 (TAMP_IN3) and PC13 (TAMP_IN1) and I want to handle both tamper pins events in linux userspace. I have achieved my goal by adding small code at plat_setup and disabling tamper in device tree. I also modified the init function in stm32_tamp so it won't reset my configuration. In addition, I also disable secure tamp to make sure that I can modify the register in linux userspace.

Inside my small code, I reset the tamp configuration first (copy from stm32_tamp_reset_register) and enable TAMP_IN1 and TAMP_IN3 by setting bit 0 and bit 2 in TAMP_CR1 register. I also set bit 0 and bit 2 in TAMP_CR2 register as I don't want to erase backup memory after tamper event. This my code snippet

/* Enable clock */
mmio_write_32(RCC_BASE | RCC_MP_APB5ENSETR, mmio_read_32(RCC_BASE | RCC_MP_APB5ENSETR) | RCC_MP_APB5ENSETR_RTCAPBEN);
 
/* unlock rtc protection */
mmio_write_32(PWR_BASE + 0x00, mmio_read_32(PWR_BASE + 0x00) | (1 << 8));
 
/* Disable all internal tamper */
mmio_write_32(TAMP_BASE + 0x00U, 0U);
 
/* Disable all external tamper */
mmio_write_32(TAMP_BASE + 0x04U, 0U);
 
/* Clean configuration registers */
mmio_write_32(TAMP_BASE + 0x0CU, 0U);
mmio_write_32(TAMP_BASE + 0x10U, 0U);
mmio_write_32(TAMP_BASE + 0x20U, 0U);
 
/* Clean Tamper IT */
mmio_write_32(TAMP_BASE + 0x2CU, 0U);
mmio_write_32(TAMP_BASE + 0x3CU, 0x009F0002U); // DO NOT CLEAR TAMP_IN3 AND TAMP_IN1
 
mmio_write_32(TAMP_BASE + 0x50U, 0U);
 
/* Enable external tamper 1 and 3 */
mmio_write_32(TAMP_BASE | 0x00U, 0x05U);
/* Set MODE */
mmio_write_32(TAMP_BASE | 0x04U, 0x05U);

At first, I am quite happy with the result as the tamper detection works well in linux userspace by reading TAMP_SR register. However, after I set PC1 and PC13 as GPIO input, I found out that PC1 value in GPIO input data register (offset 0x10) is always 0 even if the voltage level is high. It is different from PC13 as I can read the GPIO value from the input data register. Moreover, the PC1 is also capturing falling-edge events while the PC13 only captures rising-edge events with the same configuration.

So, is it possible to use PC1 as tamper pin and also as GPIO input just like PC13 pin?

Thanks in advance

[PatrickF]

Hi,

Behavior of PC1 could be explained because it is a mixed supply IO, with one input part on VSW domain (for TAMP_IN3) and one I/O part on VDD as a classic GPIO. When TAMP_IN3 is enable, the complete GPIO part is forced inactive, this explain the reading of 0.

PC13 belong completely to VSW domain, and the GPIO input path is still active when TAMP_IN1 is enabled.

In order to read the PC1 TAMP_IN1 level, solution might be connect it externally to another GPIO (with maybe some passive glue (diode) to avoid hacking the TAMP level with the GPIO output setting, or use a GPIOZ secure GPIO if you manage secure mode in your SW).

For the double edge detection on PC1, might be linked to some bounces on the signal. Did you try adding an 1 or 2nF external capacitor ? It is also possible to add filtering using TAMPFLT (notice that this need to set TAMPxTRG=1 to keep active high tamper detection).

Regards.

[jandriea]

Hi @PatrickF​ ,

Thank you so much for your clear explanation about PC1 and PC13 behavior. From your explanation, I believe that I need to disable the TAMP in order to use both pins as GPIO input in linux userspace as I only need the TAMP detection when the device is in battery mode or booting.

I already have 10nF external cap connected to PC1 pin so I will change my configuration and add filtering to the pin

Thanks for your help