Power plane in DDR layout

[Сactus]

Hello,
   I'm investigating DDR routing and for practice training to make 6 layer board with STM32MP135 and DDR - NT5CC256M16ER-EK, the similar to STM32MP135F-DK.
     Into the "DDR memory routing guidelines for STM32MP13x" everywhere recommend to use VDD_DDR polygon before Bottom layer, the same I have saw in "MB1635 Board design project files".

Could someone explain, why is important to use VDD DDR polygon before bottom layer under DDR chip?
Can I use GND layer here?