Purpose of external tamper mask, enable interrupt, non-secure masked interrupt status and secure masked interrupt status bits.

[AGamb.4]

Could you explain to me what is the purpose of the different bits associated to the tampers?

I am mainly focus on using the passive tampers of the STM32MP1 and I have seen the following configuration bits I don't fully understand:

What I understand:

• Register CR1 - TAMPxE = Enables/Disables the tamper
• Register CR2 - TAMPxTRG = In PASSIVE mode determines if the tamper is triggered in logic level 0 or 1.
• Register CR2 - TAMPxNOER = Does not erase the backup register/does not block reading of the BCKSRAM.
• Register SR - TAMPxF = Flag set when the tamper is triggered.
• Register CSR - CTAMPxF = Bit to clear the SR tamper flag.

What I am confused about:

• Register CR2 - TAMPxMSK = Does this bit stops the system to execute the interrupt and stops the backup register erasure? What is the difference between setting this to 1 and setting TAMPxIE to 0 + TAMPxNOER to 1?
• Register IER - TAMPxIE = I do understand this enables/disables the interrupt generated by the tamper triggered but I do not understand the relation with the TAMPxMSK bit.
• Register MISR - TAMPxMF = Are these just flags? Or must they be configured? What do they mean and how are they supposed to be used?
• Register SMISR - TAMPxMF = Are these the same as Register MISR but for secure context? If so

Another configuration bit I would like to clarify is "TAMPDPROT", changing this bit I could trigger the interrupt in the Secure Context in Sp-Min, but not in Non-Secure Context in Linux. This is probably because of some configuration missing in the Linux environment, How could I configure the linux to react to the interrupt? Printing a message for example...

Does the "TAMPDPROT" bit, limit the access and interaction, including the configuration registers and interrupt handler, to the secure context vs non-secure context?

Best regards,

Andrés

[Jean-Marc S]

Hello

Regarding the request to handle tamper interrupt into non secure Linux I think you may refer to below post:

https://community.st.com/s/question/0D53W000013qHGlSAM/how-detect-and-store-tamper-event-by-linux

Regarding TAMPER bits let me come back to you in the next days.

JM

[Jean-Marc S]

also..

• Register CR2 - TAMPxMSK = Does this bit stops the system to execute the interrupt and stops the backup register erasure? What is the difference between setting this to 1 and setting TAMPxIE to 0 + TAMPxNOER to 1?

The TAMPxMSK can be used in low power mode to avoid system wakeup to clear the TAMPxF flag as stated in the RM Section “Trigger output generation on tamper event�?

When TAMPxMSK bit is set, the TAMPxF flag is masked, and kept cleared in TAMP_SR

register. This configuration permits the low-power timers to be triggered automatically in

Stop mode, without requiring the system wakeup to perform the TAMPxF clearing. In this

case, the backup registers are not cleared.

• Register IER - TAMPxIE = I do understand this enables/disables the interrupt generated by the tamper triggered but I do not understand the relation with the TAMPxMSK bit.

As stated above, those are 2 different ways to use the tamper. It is either using TAMPxMASK (when in low power mode mainly) or using TAMPxIE

• Register MISR - TAMPxMF = Are these just flags? Or must they be configured? What do they mean and how are they supposed to be used?

The TAMP_MISR register is read only. So yes only flags. They are set when the corresponding interrupt is raised.

• Register SMISR - TAMPxMF = Are these the same as Register MISR but for secure context? If so

Yes same as TAMP_MISR for secure.

• Does the "TAMPDPROT" bit, limit the access and interaction, including the configuration registers and interrupt handler, to the secure context vs non-secure context?

Yes. When set to 0 only secure APB access are allowed to configure the tamper. 

JM

[Jean-Marc S]

small additional info:

the TAMP_MISR and TAMP_SMISR are flag that are only active when the iterrupt is enabled

and so are must be used in the ISR interrupt routines.

the TAMP_SR are flags that will be activated independently of the interrupt activation.

JM