Questions about setting the ADC clock on the M4 core side

[Machilus]

Hi ST

I have a question when setting the ADC Clock on the M4 Core side.

The STM32MP151C datasheet states that the ADC Clock can be set up to 36Mhz.

When the AHB clock is 200Mhz, what clock will it work with if I set "ADC ClockPrescaler" to "ADC_CLOCK_SYNC_PCLK_DIV4"?

When calculated, ADC Clock is 50Mhz.

However, the maximum operating clock in the datasheet is 36Mhz.

Which ADC clock will it work with?

I would be grateful if you could tell me the answer.

Regards

Machilus

[PatrickF]

Hello,

this setting will not work as you are above the maximum frequency.

In your case, you cannot use the 200MHz bus clock as source and you must use ADC kernel clock as ADC clock source (which could come from either pll4_r, pll3_q or per_ck). the ADC kernel clock could be up to 133MHz and ADC kernel clock divider has a much large division range which ensure you can get it within the 36MHz range..

Please refer to RefMan (RM0441 for STM32MP151C)

• RCC section "Clock distribution for HDMI-CEC, STGEN, ADCs and DACs", especially the figure "Kernel clock distribution for ADC12, DACs, STGEN and HDMI-CEC"
• ADC section "ADC clocks", especially the figure "ADC clock scheme"

Regards.