Regarding Stm32mp1 Cortex A7 Interrupt Handling.

[Sindhu Vadde]

Hi,

I am using Cortex A7 processor GIC V2 for Interrupt handling. I configured GICC and GICD both. I enabled timer and interrupt for timer also. After enabling timer i can able to see pending status in GICD but It is not routing to A7 core. For this what may be the reason?

[PatrickF]

HI @Sindhu Vadde​ ,

Did you enable the interrupt in Cortex-A7 itself (Bit I in CPSR) ? Interrupts in each core are globally masked by default.

Did you correctly set the GICD_ITARGETSRx ?

Did you tried with SGI (using GICD_SGIR) ?

Maybe read additional resources from ARM:

GIC : https://developer.arm.com/documentation/ihi0048/lates

Cortex-A7 : https://developer.arm.com/documentation/ddi0464/latest/

ARMv7-A architecture: https://developer.arm.com/documentation/ddi0406/latest/

Regards.

[Sindhu Vadde]

Hi,

Thanks for the reply.

Did you correctly set the GICD_ITARGETSRx ?

we are setting 0x01010101 values in GICD_ITARGETSRx.

Did you tried with SGI (using GICD_SGIR) ?

yes I tried software interrupt is working fine.

You can see the values for GICD and GICC registers in below attachments.

[PatrickF]

Hi,

as GIC and Cortex-A7 are pure ARM IPs, there is nothing related to STM32MP1 which could avoid to get interrupts once they are visible/pending on GIC.

To check what could be your issue in bare-metal, you could have a look to related TF-A drivers, e.g. https://github.com/STMicroelectronics/arm-trusted-firmware/tree/v2.6-stm32mp/drivers/arm/gic

Maybe ask directly ARM or seek some other project using Cortex-A7 (I found https://github.com/4ms/stm32mp1-baremetal, but we cannot give any advice on it)

Regards.

[Sindhu Vadde]

Hi,

We are already contacted ARM people. But they said that contact ST people for more information. You can find My case in ARM community through below link.

Case: 00469918 (arm.com)

[PatrickF]

Hi,

as SGI are working, the issue is only to set GIC correctly, but I have not more knowledge than you as root source of information is ARM documentations.

If you are building bare-metal SW from scratch, you will have hard time to get it mature. Cortex-A processor are quite complex to manage (not only interrupt, but also MMU, security, peripherals, etc...).

This explain why many people uses existing ecosystems (e.g.OpenSTLinux) to benefit from hundredths of man*years of development and open-source SW maintained by the community.

As interrupts are working in the STM32MP1 hardware with our deliveries, we cannot help more than providing link to ARM documentation and link to our existing deliveries such as TF-A or else.

If your project has significant volume, maybe you could try to get help from your local ST support.

Regards.

[Genadi Zawidowski]

Check GICInterface->PMR register, THis value should be greaer then prority of interrupt.

Bay the way, each core has own GICInterface->PMR and GICDistributor->IPRIORITYR

just for your information, ARM cmsis_5 provide wrappers for CP15 and GIC registers,

[Sindhu Vadde]

Hi,

I have checked priority registers. I kept same priority for SGI and timers It's working fine. I can able to see Pending status in GICD for UART. But it is not going to IRQ handler.