Regarding Stm32mp157a Peripheral Allocation to Each Core?

[Sindhu Vadde]

Hi,

We are using stm32mp157a processor. We have some confusion for peripheral allocation for 3 cores. We referred document new microprocessor series with enhance performance thanks to its multicore architecture and graphical processor. from wiki.

Below are the points we are unable to understand.

1.UART1, I2C4, I2C6, SPI6 allocation not clear. These peripherals are not specified for which core they are allocated.

2.If Some peripherals are sharable, how can i allocate to each core and how can i disable sharable peripheral to particular core.

3.How can i find out privileged mode of processor.

4.How can i disable secure mode for each processor in SCR register.

[PatrickF]

I @Sindhu Vadde​ ,

I guess these wiki will answer most of your questions regarding SW choices related to peripheral allocation.

https://wiki.st.com/stm32mpu/wiki/STM32MP15_peripherals_overview

https://wiki.st.com/stm32mpu/wiki/How_to_assign_an_internal_peripheral_to_a_runtime_context

For 3) and 4), I think this is managed by TF-A/OpTee/etc... transparently to user. HW behavior is related to Cortex-A7 and documentation to be found on ARM side.

Regards.