RFI regarding BGA package pin delays for the DDR3 and the EMMC interfaces

[AronBan]

Hello,

We are designing a custom board with the "STM32MP157FAC1" MPU.
Would it be possible to get the die to BGA package pin delays for the DDR3 and the EMMC interfaces ?

The AN5122 seems to only have track lengths. Our PCB track layout has some constraints that prevent us from completely copying the reference design layout for DDR. Another post mentioned an Excel table but can't find it in the documentation page for the IC.

Thank You.
Aron.

[PatrickF]

Hi @AronBan ,

You could find DDR routing examples as well as DDR excel files to check your PCB track lengths Vs guidelines in the following file: STM32MP15x Series DDR memory routing guidelines examples

(I must admit it is not easy to locate it from website)

Nothing for eMMC were package length skew could be ignored.

Regards.

[AronBan]

Hi @PatrickF 

Thank you for providing this information.

Would it be possible to get the equalization in delays ?

Not all traces in the DDR interface Bytes are able to be routed in a single layer. Hence we will have to consider propagation delays through vias. Would be nice to embed the pin package delays in the Altium Footprint to increase reliability of the system.

Kind Regards,