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Osamu
Visitor II
March 4, 2020
Question

SDIO clock on the STM32MP157A-EV1

  • March 4, 2020
  • 2 replies
  • 1817 views

I'm using STM32MP157A-EV1.

It configured boot from eMMC mode.

This is because SDIO is used as interface.

I inserted the uSD card into the slot for trial.

The information of SDIO is as follows.

root@stm32mp1:~# cat /sys/kernel/debug/mmc0/ios

clock:     99000000 Hz

actual clock:  99000000 Hz

vdd:      17 (2.9 ~ 3.0 V)

bus mode:    2 (push-pull)

chip select:  0 (don't care)

power mode:   2 (on)

bus width:   2 (4 bits)

timing spec:  6 (sd uhs SDR104)

signal voltage: 1 (1.80 V)

driver type:  0 (driver type B)

When the same uSD card is inserted in another company's evaluation board, it is as follows. (CPU is Cortex A53)

root@localhost:/home# cat /sys/kernel/debug/mmc0/ios

clock:     208000000 Hz

actual clock:  200000000 Hz

vdd:      21 (3.3 ~ 3.4 V)

bus mode:    2 (push-pull)

chip select:  0 (don't care)

power mode:   2 (on)

bus width:   2 (4 bits)

timing spec:  6 (sd uhs SDR104)

signal voltage: 0 (1.80 V)

driver type:  0 (driver type B)

There are large differences in clocks.

STM32MP157A-EV1: 99000000 Hz

Other board: 200000000 Hz

Is it possible to set 200MHz with STM32MP157A-EV1?

Or is it impossible due to hardware limitations?

Best Regards,

Osamu

    This topic has been closed for replies.

    2 replies

    P
    PatrickF
    Technical Moderator
    March 4, 2020

    This 99MHz is a choice for Starter package as on EV1 board there is many constrains to define an 'average' clock tree suitable for all peripherals available on that board.

    It also allow to trial the DDR50 (49.5MHz clock DDR data) on the SD-Card without changing the clock tree.

    As per DS12505 and AN5031, the HW limitation for the SDMMC clock is around 133MHz for the SDMMC clock (using VDD=3.3V and an external level translator to support UHS modes). The SD-Card standard define UHS SDR104 to max 208MHz clock.

    You could change the clock tree configuration using CubeMX and tune it to your system requirements (while keeping frequencies below datasheet values, so ~133MHz for SDMMC clock).

    Note that increasing interface clock speed of the SD-Card does not usually translate directly in same data transfer bandwidth increase (due to driver overhead, filesystem processing and SD-Card device itself).

    O
    OsamuAuthor
    Visitor II
    March 17, 2020

    Dear PatrickF,

    Thank you for your explain and I'm sorry for my late response.

    >>the HW limitation for the SDMMC clock is around 133MHz for the SDMMC clock (using VDD=3.3V and an external level translator to support UHS modes).

    I think the VDD of UHS mode is 1.8V. But is it necessary to convert to 3.3V to use UHS mode with STM32MP157A-EV1?

    Best Regards,

    Osamu Murakami

    P
    PatrickF
    Technical Moderator
    March 17, 2020

    For SD-Card, you should respect the standard.

    SD-Card always uses a 3.3V (2.7 - 3.6V) supply and always start communicating using 3.3V IO signaling voltage (used for default speed and high speed modes). After negotiating for a supported UHS mode, there is a specific sequence (ACMD41, CMD11) to switch the card IO signaling voltage to 1.8V (but card supply remain at 3.3V). If you don't do the IO voltage switch after CMD11, the card will stop working (this is required in the standard).

    This explain the need for a level translator with configurable IO supply on SD-Card side (See STM32MP157C-EV1 board schematic for an example)

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