SPL Initialize Error on DDR Ram speed
Hello,
I am trying to bring up a custom board based on the STM32MP157D MPU via SDCard.
I am using u-boot 2022-01-rc3 as bootloader and the boot is using SPL (I have an SDCard with a GPT Partition table with fsbl1, fsbl2 and ssbl named partitions).
This is the 2nd time I am using this u-boot to bring up a custom STM32MP15x board.
The first time was using a STM32MP151a and I needed to activate the clock tree for the USART1 and modified the low level setup in the stm32mp1_clk source code to enable the USART1 clocks and to activate the serial port #1 to have the SPL ready to print as soon it starts.
But now, something goes wrong. I am using a DDR3 layout as the ED1 evaluation kit as 2x4GB (2x16 bit) 533Mhz DDR RAM. Using the same clk initialization stuff in the ddr3-1066-888-bin-g-2x4gb-533mhz device tree file, and the rcc configuration as follow:
&rcc {
status = "okay";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_DISABLED
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_LSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
u-boot,dm-pre-reloc;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};it fails with:
U-Boot SPL 2022.01-rc3 (Aug 04 2022 - 17:01:02 +0200)
RAM: EK470 DDR3-DDR3L 32bits 533000kHz
stm32mp1_clk rcc@50000000: stm32mp1_clk_disable: id clock 228 has been disabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 220 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 222 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 226 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 229 has been enabled
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 224 has been enabled
id=15 clock = 1fc4ef40 : 533000 kHz
stm32mp1_clk rcc@50000000: computed rate for id clock 224 is 533000000 (parent is PLL2_R)
stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 228 has been enabled
get_ram_size(c0000000, 40000000)
info.size: 4
DDR invalid size : 0x4, expected 0x40000000
DRAM init failed: -22
### ERROR ### Please RESET the board ###I suppose the ddr3 setup file in u-boot dts is using the right setup of memory (as the ed1 board I suppose it is working fine), so I cannot understand why the get_ram_size() function returns a single 32 bit (4 bytes) size.
Can help you out to jump over this issue?
Can be a wrong voltage on the DRAM chips?
Regards,
Gianluca