STM32MP1 Eval - Hyperlynx DDR Wizard Odt Model

[gokhannsahin]

Hi everyone,

I have tried to check eval board PCB with hyperlynx DDR wizard but I can't.

I downloaded all of the IBIS data which are Nanya DDR3L ram and MP157A.

However, I'm confused about which ODT models I should choose.

Please help me which model I chose to pass this check.

By the way, I attached the odt model page screen.

[PatrickF]

Hi,

With a DDR3L you can set the values below for your simulation:

In write mode (ODT disabled on STM32MP1 side, ODT enabled on memory side)

• Controller (STM32MP1) model are :
  • DQ and DM are MSD_D3RP3L_48
  • DQS is MSD_D3RF3L_48
  • CLK is defined PDDRIO_PAD, select MSD_D3RP3L_48
  • address and control are MSD_D3RP3L_48

• DDR model is set with ODT 60 and frequency 1066.

In read mode (ODT enabled on STM32MP1 side, disabled on memory side)

• Controller (STM32MP1) model are :
  • DQ and DM are MSD_D3RP3L_ODT60
  • DQS is MSD_D3RF3L_ODT60

• DDR model is set with Zout 40 ohm and frequency 1066

Regards,

[gokhannsahin]

How did you identify them? If I change parameters in CubeMX, do I need to change them too?

Also, when ODT is disabled, for DRAM, DQS40_ODT_60_1066 is right?

I attached the config image, is right?

If yes, it fails;

Also, Hyperlynx gives a warning about MP1 Ibis data.

[PatrickF]

Hi,

info in the IBIS file itself,

There are one description for the IO PDDRIO_PAD (for all single ended IOs and CLK/CLK#) and one description for the differential PDIFF_PAD (DQS)

e.g.

[Model Selector] PDDRIO_PAD

MSD_D3RP2_18 DDR2 MSD_D3R_PDDRIO Z0=18-Ohm

MSD_D3RP2_40 DDR2 MSD_D3R_PDDRIO Z0=40-Ohm

MSD_D3RP2_48 DDR2 MSD_D3R_PDDRIO Z0=48-Ohm

MSD_D3RP2_ODT150 DDR2 MSD_D3R_PDDRIO cell 150-Ohm ODT Receiver

MSD_D3RP2_ODT50 DDR2 MSD_D3R_PDDRIO cell 50-Ohm ODT Receiver

MSD_D3RP2_ODT75 DDR2 MSD_D3R_PDDRIO cell 75-Ohm ODT Receiver

MSD_D3RP2_ODTOFF DDR2 MSD_D3R_PDDRIO cell ODT off Receiver

MSD_D3RP3_34 DDR3 MSD_D3R_PDDRIO cell Z0=34-Ohm

MSD_D3RP3_40 DDR3 MSD_D3R_PDDRIO cell Z0=40-Ohm

MSD_D3RP3_48 DDR3 MSD_D3R_PDDRIO cell Z0=48-Ohm

MSD_D3RP3L_34 DDR3L MSD_D3R_PDDRIO cell Z0=34-Ohm

MSD_D3RP3L_40 DDR3L MSD_D3R_PDDRIO cell Z0=40-Ohm

MSD_D3RP3L_48 DDR3L MSD_D3R_PDDRIO cell Z0=48-Ohm

MSD_D3RP3L_ODT120 DDR3L MSD_D3R_PDDRIO cell 120-Ohm ODT Receiver

MSD_D3RP3L_ODT40 DDR3L MSD_D3R_PDDRIO cell 40-Ohm ODT Receiver

MSD_D3RP3L_ODT60 DDR3L MSD_D3R_PDDRIO cell 60-Ohm ODT Receiver

MSD_D3RP3L_ODTOFF DDR3L MSD_D3R_PDDRIO cell ODT off Receiver

MSD_D3RP3_ODT120 DDR3 MSD_D3R_PDDRIO cell 120-Ohm ODT Receiver

MSD_D3RP3_ODT40 DDR3 MSD_D3R_PDDRIO cell 40-Ohm ODT Receiver

MSD_D3RP3_ODT60 DDR3 MSD_D3R_PDDRIO cell 60-Ohm ODT Receiver

MSD_D3RP3_ODTOFF DDR3 MSD_D3R_PDDRIO cell ODT off Receiver

MSD_D3RPL2_34 LPDDR2 MSD_D3R_PDDRIO cell Z0=34-Ohm

MSD_D3RPL2_40 LPDDR2 MSD_D3R_PDDRIO cell Z0=40-Ohm

MSD_D3RPL2_48 LPDDR2 MSD_D3R_PDDRIO cell Z0=48-Ohm

MSD_D3RPL2_60 LPDDR2 MSD_D3R_PDDRIO cell Z0=60-Ohm

MSD_D3RPL2_80 LPDDR2 MSD_D3R_PDDRIO cell Z0=80-Ohm

MSD_D3RPL2_ODTOFF LPDDR2 MSD_D3R_PDDRIO cell ODT off Receiver

MSD_D3RPL_48 LPDDR MSD_D3R_PDDRIO cell Z0=48-Ohm

MSD_D3RPL_ODTOFF LPDDR MSD_D3R_PDDRIO cell ODT off Receiver

The simulation impedance should match the register config.

The ODTs impedance is programmable via ZQ0CR1.ZPROG[7:4]. Default and recommended value is 48 ohms.

The DQ/DQS output impedance is programmable via ZQ0CR1.ZPROG[3:0]. Default and recommended value is 60 ohms.

See also AN5168

Regards.

[gokhannsahin]

Updated last post with failed and configuration, please check me.

[PatrickF]

Note that I'm not expert of Hyperlynx simulation, but in my opinion, this tool is used to check the signal integrity, power integrity of your PCB like routing, decoupling, ground planes, terminations, stubs, etc...

I'm not sure it should be used to define or verify CubeMX DDRPHY controller parameters.

Regards.

[PatrickF]

This post: https://community.st.com/s/question/0D53W000008jQNZ could help you

[gokhannsahin]

Your ref guide gives Ron and ODT the following image, why do we use 60ODT and 48R?