STM32MP1: SPI transfer has delay every eight bytes

[Dat Tran]

Hi, on SPI, does anyone know why every 8 bytes then it has a big gap?

We tried:

1MH, no gap,

2MH, gap occurs,

4MHz gap bigger,

8MH gap bigger than 4MHz

Seem higher frequency, bigger gap 

We don't use DMA

 

 

 

[AScha.3]

Hi,

i think, you see just the effects of cache/fifo and hi-speed cpu vs. fixed hardware timing :

when spi speed low, all (whatever you do in code) the cpu can execute before next spi packet coming,

so "seems" continuous stream.

If now spi is finished fast, you see the time, the cpu needs between the spi packets.

So use slow timing, then it can prepare data between the packets and is ready for next packet without a "gap".

Or make your code more optimized/faster ; 8MHz x 8 byte is 8 us - not so much time . 

Or use dma, then you have the 8 us to prepare the next data, while the dma is busy with transmitting.

And you have optimizer set to..?  (I recommend -O2 )

[PatrickF]

Hi @Dat Tran 

depending on the used SPI instance, the FIFO is 8 or 16 bytes, so the behavior sound normal if you are using Linux which is far to ensure real time.

Either use DMA or move time critical peripheral management on Cortex-M4 side (if you are using STM32MP15x).

Regards.

[Dat Tran]

Thank PatrickF,