STM32MP135 - issue with 4 bits moved to different address when testing DDR

[tomeko]

Hello,

I'm testing a prototype board with STM32MP135FAE7 and MT41K256M16TW-107 DDR3L, using STM32DDRFW-UTIL firmware.

DDR_Test_Random fails if memcpy (DDR -> DDR) is used inside this test (this is the only one test using memcpy) but not if I'm copying memory using plain C loop with pointers to volatile uint32_t or volatile uint64_t. Failure type seems pretty consistent: 4 consecutive bits (one, always the same nibble) are "moved" from one 16-bit word to the next one. As far as I know (but I'm not 100% sure) this particular PCB data traces are uniform and relatively short (~28 mm), though one detail that might be more unusual is that order of data bits between MPU and DDR is swapped to help with routing.

I've used default memory settings from this example (DDR model is matching), I've tried also relaxed timings from CubeMX and lowering memory clock but this issue was persistent.

Do you have any hints how to debug this issue and what could be possible cause?

 

[PatrickF]

Hi @tomeko 

Did your design follows AN5692 - DDR memory routing guidelines for STM32MP13x product lines ?

Did you have 100 ohms termination resistor on CLK/CLK# ?

Any issue with DQS or DM wrongly swapped ?

Are PCB signal length ok with the package you are using thanks to the excel sheet provided in Examples of DDR memory routing on STM32MP2 MPUs?

Regards

[tomeko]

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@PatrickF wrote:

Any issue with DQS or DM wrongly swapped ?

Thanks for reply, this led me to a very probable issue - data bits were mixed too much. Not just lower/upper byte or bits within bytes, but each byte bus from MPU was connected with half of lower and half of upper DDR byte bus.