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Michael Schmid
Visitor II
December 10, 2022
Solved

STM32MP157 - memory for the M4 core

  • December 10, 2022
  • 3 replies
  • 2613 views

Dear experts.

​

we plan to use a STM32MP157, where the A7 core should have 512MB DDR RAM, and theM4 core 16 MB. What options exists, to give the M4 core that 16 MB of RAM?

  • From the DS, i understand that the DDR RAM of the A7 is not accessible for the M4. Is that right?
  • external QSPI PSRAM, would be low cost and low pin count. From the DS, the QSPI interface is only for Flash, not for PSRAM?
  • external SRAM/SDRAM via the FMC? Could the M4 core occupy the FMC, while the A7 core using DDR?
  • external SPI RAM, would be the slowest variant, but should be always possible.

Is there an application note, showing how more then a MB RAM is added to the M4 core in an STM32MP15x?

Best regards,

Michael

    This topic has been closed for replies.
    Best answer by PatrickF

    Hi @Michael Schmid​ 

    please have a look to https://wiki.st.com/stm32mpu/wiki/Exchanging_buffers_with_the_coprocessor

    Note that this stand only for Data. Code should reside in SRAMs/RETRAM as Cortex-M4 performance execution penalty for running code from external memory will be extremely high (has there is no caches and bus paths are not optimized for that).

    Regards.

    In order to give better visibility on the answered topics, please click on 'Select as Best' on the reply which solved your issue or answered your question. See also 'Best Answers'

    3 replies

    K
    KnarfB
    Super User
    December 10, 2022

    > From the DS, i understand that the DDR RAM of the A7 is not accessible for the M4. Is that right?

    No, you can assign some DDR RAM space for M4 code and data. This is actually the standard way, the M4 is considered a Linux coprocessor that is booted from Linux (or the bootloader). See https://wiki.st.com/stm32mpu/wiki/Arm_Cortex-M4 and or the STM32MP157 DK2 board schematics

    hth

    KnarfB

    P
    PatrickFAnswer
    Technical Moderator
    December 12, 2022

    Hi @Michael Schmid​ 

    please have a look to https://wiki.st.com/stm32mpu/wiki/Exchanging_buffers_with_the_coprocessor

    Note that this stand only for Data. Code should reside in SRAMs/RETRAM as Cortex-M4 performance execution penalty for running code from external memory will be extremely high (has there is no caches and bus paths are not optimized for that).

    Regards.

    In order to give better visibility on the answered topics, please click on 'Select as Best' on the reply which solved your issue or answered your question. See also 'Best Answers'

    A
    Alex - APMemory
    Explorer
    October 10, 2023

    Hi,

    just one comment about QSPI / SPI, even it might be limited BW.

    QSPI Memory controller is designed for NOR as you mentionned. QSPI PSRAM could be used, but controller doesn't support Memory mapped write. APS1604M..., APS6404L..., APS12804O... IoT RAM are example of SPI & QSPI PSRAM (in SOP8/USON8/WLCSP).

    Alex

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