STM32MP157c changing pll4q clock speed problem!

[aliMesut]

Hello,

I am working stm32mp157c. I'm trying to change the clock rate of stmcubeide using pll4q for spi45 (StmCubeIde outputs are attached.). Also The bsp setting is attached .

Pll settigs is;

   st,pll@3 {

      reg = <3>;

      cfg = <1 32 5 66 5 PQR(0,1,0)>;

      frac = <0x1000>;

   };

I see the clocks are set correctly except pll4q (in linux "cat /sys/kernel/debug/clk/clk_summary" command).

It turns out 25.125Mhz when it should be 6MHz (linux outputs are attached).

I measure the pll4q clock with oscilloscope. Same as the value i see in "cat /sys/kernel/debug/clk/clk_summary" (not 6MHz, it is 25.125Mhz).

Where do you think the problem might be?

[TDK]

I've changed the tag from STM32 MCUs to STM32 MPUs.

[PatrickF]

Hi,

sound your effective value for DIVQ is 15 (divide by 16) instead of 66 (divide by 67). 402/16 = 25.125 MHz.

Any chance there is somewhere in your DT an entry which override the 66 value by 15 ?

Please confirm the PLL4 is running at 402MHz :

	cat /sys/kernel/debug/clk/clk_summary | grep pll4 -A 20 -m 1

Then need to confirm the effective DIVQ value (need to install devmem2 using "apt-get update" then "apt-get install devmem2")

Read RCC_PLL4CFGR2, DIVQ is on bits 14-8

devmem2 0x5000089C W

if ok check other PLL settings (RCC_PLL4CR, RCC_PLL4CFGR1, RCC_PLL4FRACR

devmem2 0x50000894 W
devmem2 0x50000898 W
devmem2 0x500008A0 W

Regards.

[aliMesut]

Hi @PatrickF​ ,

Previously, I changed the settings as follows;

st,pll@3 {

reg = <3>;

cfg = <1 39 5 79 5 PQR(0,1,0)>;

};

In this case, pll4 vco becomes 480mhz (i checked cat /sys/kernel/debug/clk/clk_summary | grep pll4 -A 20 -m 1 command). pll4q should be 6 mhz but it is 24 mhz.

1. devmem2 0x5000089C W -> read value is 0x00051305
2. devmem2 0x50000894 W -> read value is 0x00000023
3. devmem2 0x50000898 W -> read value is 0x01010027
4. devmem2 0x500008A0 W -> read value is 0x00010000

But I did not understand what conclusion to draw from these data.

Regards.

[PatrickF]

Hi,

I have reproduced on my side and escalated to development team.

I will try to come back to you asap.

As there is divider inside SPI, there is usually no need of such high division factor in PLL.

Meanwhile, may I suggest to use an higher pll4q frequency and divide the clock inside SPI (or other related peripherals) ?

Regards.

[aliMesut]

Hi @PatrickF​ ,

• I disabled ltdc in kernel and uboot but the problem is not solved.
• I want to change the clock of spi4 while the code is running. Clocks other than PLL4Q are connected to other peripherals.That's why I can't get other clocks.
• I will change x in next revision.

But I couldn't understand why it didn't happen when I disabled ltdc and dsi from the kernel.

Regards.