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BillR
Visitor II
March 10, 2022
Solved

STM32MP157C with MII PHY not working

  • March 10, 2022
  • 2 replies
  • 2124 views

I am using a KSZ9021GN PHY in MII mode. Due to supply chain issues we had to resort to this PHY. (Cube MX says I can't use GMII mode).

I am experiencing this apparently common issue: 

[ 15.650981] dwmac4_dma_reset err
[ 15.652849] stm32-dwmac 5800a000.ethernet: Failed to reset the dma
[ 15.659006] stm32-dwmac 5800a000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 15.668518] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Hw setup failed

I have read over https://wiki.st.com/stm32mpu/wiki/Ethernet_overview#How_to_debug

and it says typically that the clock(s) are not present at reset, but I am not clear on what clocks are involved in MII mode.

Any thoughts on what might be wrong?

    This topic has been closed for replies.
    Best answer by PatrickF

    Hi @BillR​ ,

    from your schematics abstract, I see a major issue (which explain your error message):

    • PHY TX_CLK is not connected.
    • PHY TX_CLK output (2.5/25MHs clock) should be connected to STM32MP1 pin ETH_TX_CLK (which is an input).
    • PHY GTX_CLK input is useless in MII mode.

    In addition, few points to be double checked/corrected:

    • COL, CRS, TX_ER and RX_ER are usually connected to the MAC in MII mode.
    • PG5 ETH_CLK_125 is useless in MII mode (only for GMII) and could be disconnected and disabled on the PHY mode strapping
    • PHY TX_CLK direction is wrong on your device schematics library (it is an output)

    Once those HW issues are ok, if you still have issues, please share your Ecosystem version and DT config for further analysis.

    Regards,

    2 replies

    P
    PatrickFAnswer
    Technical Moderator
    March 10, 2022

    Hi @BillR​ ,

    from your schematics abstract, I see a major issue (which explain your error message):

    • PHY TX_CLK is not connected.
    • PHY TX_CLK output (2.5/25MHs clock) should be connected to STM32MP1 pin ETH_TX_CLK (which is an input).
    • PHY GTX_CLK input is useless in MII mode.

    In addition, few points to be double checked/corrected:

    • COL, CRS, TX_ER and RX_ER are usually connected to the MAC in MII mode.
    • PG5 ETH_CLK_125 is useless in MII mode (only for GMII) and could be disconnected and disabled on the PHY mode strapping
    • PHY TX_CLK direction is wrong on your device schematics library (it is an output)

    Once those HW issues are ok, if you still have issues, please share your Ecosystem version and DT config for further analysis.

    Regards,

    B
    BillRAuthor
    Visitor II
    March 10, 2022

    Patrick, thanks for the fast response. This major issue you described was starting to dawn on me just as you replied. We need to respin the board anyway and will take all these changes into account. Thanks a lot!

    Bill.

    P
    PatrickF
    Technical Moderator
    March 10, 2022

    Hope that it will run smoothly then.

    (maybe you could already try by removing R101 and connecting signal to PHY pin 57)

    Regards,

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