STM32MP257F-EV1 PCIe *Endpoint Mode*

[RJEdell]

How may I use STM32MP257F-EV1 PCIe in *Endpoint Mode*?  I am looking to connect two STM32MP257F-EV1 devices together via PCIe; one device in PCIe host mode, and the other in PCIe endpoint mode.

1) Physical connection

According to the boards user manual, I see that the PCIe interface is presented on CN13 and described as a Mini-PCIe.  How can I connect two STM32MP257F-EV1 devices together via PCIe?

2) Clock configuration

Section 8.9.1 talks about a 100MHz Ref Clock options.  There appear to be three options: (1) SOC generates a clock, (2) SOC takes external clock from U33, or (3) SOC takes clock from the mini-PCIe connector.  The selection of an option refers to several "R###" on/off choices.  Are these choices made by adjusting surface mount resistors?

If we aim to connect one eval board ("Host mode") to another ("Endpoint mode"), should we aim to bring bring board's clock to the other?  Or provide same external clock to both boards?

Where is this external clock input (U32) documented?

3) Endpoint Framework

The PCIe guide (https://wiki.st.com/stm32mpu/wiki/PCIe_overview#How_to_use_the_endpoint_framework) describes how use work with Linux PCIe framework.  The section for endpoint framework says "Coming Soon".  Do you have additional guidance elsewhere?  

 

[RJEdell]

Update regarding clock configuration questions:

I found U33 on the board.  It appears to be an oscillator, not a connector.  (Also, I mistyped U33 as U32 once in my first posting.)

I have found other PCIe reference material. It appears that I ought to be configuring the endpoint device to accept clock from the host device.  Clock option 2 ("SOC takes external clock from U33") is the board default and it seems reasonable that the board default would be designed to work with a common case of a PCIe endpoint device (imagine a wifi card) plugged into the evaluation board. Clock option 3 ("SOC takes clock from the mini-PCIe connector") seems appropriate for the eval board funstioning in the PCIe endpoint mode.  Correct?

I found several surface mount resistors labelled "R###", and the unmodified board seems to align with the user manual's statement for clock option 2:

Or by an external 100 MHz clock generator (U33):

• R87, R88, R89, and R90 ON,

• R77, R78, R288, and R328 OFF.

This is the default configuration on the MB1936 board

And so on my eval board functioning as end point, I want to alter the configuration to option 3:

Or by a device plugged into the mini‑PCIE connector:

• R77, R78, R87, R88, R89, and R90 OFF,

• R288 and R328 ON.

Which means for my endpoint mode eval board I will need to:

Remove resistors: R87, R88, R89, and R90
Add resistors: R288 and R328

Correct?

I can find the R87-R90, but I can't find R288 or R328.  Any pointers to find these two resistors?

 

[RJEdell]

(Let's see if I get another badge for replying to my own post, a second time...)

I found R277 and R328.  They are not in the board photographs in the user manual, but they are on the board I have in my lab!

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My pending queries:

1) how to physically connect two boards.  It does appear that I need "crossover-like" cable to connect "host tx" -> "endpoint rx", "endpoint tx" -> "host rx", and "host refclock" -> "endpoint refclock".  How do we manage this?

2) Am I correct about modifying just the "endpoint role" board with removing/adding the specified resistors?

3) Is there additional guidance for "endpoint mode" to fill in where https://wiki.st.com/stm32mpu/wiki/PCIe_overview#How_to_use_the_endpoint_framework says "coming soon"?

[Steven-LIN]

Hi,

I have the same question. I tried to perform an EndPoint test by following this article, but I encountered the following error message:

# ln -s functions/pci_epf_test/func1 controllers/48400000.pcie-ep/
[ 202.765232] stm32-ep-pcie 48400000.pcie-ep: No free inbound window
[ 202.765885] pci_epf_test pci_epf_test.0: Failed to set BAR4
[ 202.772564] stm32-ep-pcie 48400000.pcie-ep: No free inbound window
[ 202.777598] pci_epf_test pci_epf_test.0: Failed to set BAR5
[ 202.783326] pci_epf_test pci_epf_test.0: Failed to get private DMA rx channel. Falling back to generic one

# echo 1 > controllers/48400000.pcie-ep/start
[ 253.568783] stm32-ep-pcie 48400000.pcie-ep: Phy link never came up
[ 253.569432] stm32-ep-pcie 48400000.pcie-ep: PCIe cannot establish link: -110
[ 253.576420] pci_epc 48400000.pcie-ep: failed to start endpoint controller
sh: write error: Invalid argument

 

I was wondering if you have done any follow-up testing on this?