Support RTL8211E-VB-CG in STM32MP157

[aman.32]

We designed our own board and use RTL8211E instead of RTL8211EG-VB-CG. We are unable to get the PHY device to respond although we copy the same circuit from the MB1262. The MAC is working but the communication to Realtek PHY seems to be a problem. Does the current kernel build support RTL8211E?

[PatrickF]

As far as I know, there is no SW difference between 8211E (48 pins) and 8211EG (64 pins).

Please check your HW setting Vs PHY datasheet (PHY address, clock delay, SELRGV, etc..) and schematics.

[aman.32]

Thank you for the reply. We struggled to get RTL8211E to work. The LEDs on the RJ45 module are ON when ethernet cable is plugged in. The console message shows link is up: "stm32-dwmac 5800a000.ethernet eth0: Link is Up - 1Gbps/Full".

Nevertheless, we are unable to get the ethernet IP address after bootup. The ifconfig command shows:

eth0     Link encap:Ethernet HWaddr 7E:C4:83:84:DF:A8

         inet6 addr: fe80::7cc4:83ff:fe84:dfa8/64 Scope:Link

         UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1

         RX packets:0 errors:0 dropped:0 overruns:0 frame:0

         TX packets:10 errors:0 dropped:0 overruns:0 carrier:0

         collisions:0 txqueuelen:1000

         RX bytes:0 (0.0 B) TX bytes:1068 (1.0 KiB)

         Interrupt:57 Base address:0x8000

Any idea how we should debug it. We use the SD image we generated and run on MB1272 board, ethernet is working fine.

[PatrickF]

Maybe a clue: MB1272 (STM32MP157C-DK2) uses RTL8211F, which might deserve some changes in DT Vs RTL8211EG which is used in STM32MP157C-EV1.

If you received 0 bytes, looks like your receive path is broken. Please check the pin definition/muxing in DT, receive clock settings in the PHY and the RCC, as well as connection/timings configurations at PHY level.

[aman.32]

The dts file seems OK. The only difference ( in my hardware) is interrupt. I routed the interrupt pin to different location but cannot find anywhere to modify it.

How can I disable interrupt in the DTS file? I don't get any error in the RX/TX clock. I forced the driver to 100Mbps but IP problem persists:

[   1.530477] stm32-dwmac 5800a000.ethernet: PTP uses main clock

[   1.534880] stm32-dwmac 5800a000.ethernet: no reset control found

[   1.541052] stm32-dwmac 5800a000.ethernet: No phy clock provided...

[   1.548369] stm32-dwmac 5800a000.ethernet: User ID: 0x40, Synopsys ID: 0x42

[   1.554156] stm32-dwmac 5800a000.ethernet:  DWMAC4/5

[   1.559155] stm32-dwmac 5800a000.ethernet: DMA HW capability register supported

[   1.566391] stm32-dwmac 5800a000.ethernet: RX Checksum Offload Engine supported

[   1.573710] stm32-dwmac 5800a000.ethernet: TX Checksum insertion supported

[   1.580571] stm32-dwmac 5800a000.ethernet: Wake-Up On Lan supported

[   1.586787] stm32-dwmac 5800a000.ethernet: TSO supported

[   1.592107] stm32-dwmac 5800a000.ethernet: Enable RX Mitigation via HW Watchdog Timer

[   1.599948] stm32-dwmac 5800a000.ethernet (unnamed net_device) (uninitialized): device MAC address 8a:fd:35:fc:50:e1

[   1.610443] stm32-dwmac 5800a000.ethernet: TSO feature enabled

[   2.851618] stm32-dwmac 5800a000.ethernet eth0: No Safety Features support found

[   2.858953] stm32-dwmac 5800a000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported

[   2.867578] stm32-dwmac 5800a000.ethernet eth0: registered PTP clock

[   8.078825] stm32-dwmac 5800a000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off

[PatrickF]

Did you look at AN5031 ?

Could you share your schematics around Ethernet PHY ? If sensitive information, you could use Private Message.

[aman.32]

Yes. We follow AN5031 to implement our RTL8211E (Figure 47) except the interrupt is tied to different GPIO and PMEB is floating. I was not successful in disable the interrupt routine in the STM driver. I also sent the schematic to you directly. Thank.