Unable to set DDR clock

[jvog.sen]

Hello,

I am having a hard time setting the DDR clock at pll2 for an stm32mp157.

The clock has been configured to 528MHz using CubeMX. I checked cfg for pll2 in the DeviceTree against the Datasheet / Referance Manual and all settings seem correct.

Yet /sys/kernel/debug/clk/clk_summary returns 533MHz for pll2_r.

PLL2 gets 24MHz from HSE. My current configuration for tf-a:

&rcc {
	...
	pll2:st,pll@1 {
		compatible = "st,stm32mp1-pll";
		reg = <1>;
		cfg = < 2 65 1 1 0 PQR(1,0,1) >;
		frac = < 0x1400 >;
	};
	...

PLL2 gets configured in the dts-file for tf-a only. For kernel and u-boot there are only empty rcc-nodes:

&rcc{
	u-boot,dm-pre-reloc;
	status = "okay";
 
	/* USER CODE BEGIN rcc */
	/* USER CODE END rcc */
};

Any ideas?

[PatrickF]

Hi @jvog.sen​ ,

you device tree setting are showing 533MHz, let's decode the "cfg = < 2 65 1 1 0 PQR(1,0,1)" :

you have a frac value defined which mean the VCO frequency is

PLL input clock is 24 / (2+1) = 8MHz

PLL multiplier is (65+1)+0x1400/0x2000 = 66.625

So, VCO = 8 * 66.25 = 533 MHz

DDR clock is same as R divider is equal to 1 (0+1).

Just remove the 'frac' line if you want to go to 528MHz (please check it is set to 0 in CubeMX)

Regards

[jvog.sen]

Thank you so much! I must admit, I completely ignored the frac line all the time:unamused_face:

[PatrickF]

That's part of common pitfall on such complex product.

Regards.

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