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Graduate
October 26, 2020
Question

What if M4 RAM is too small?

  • October 26, 2020
  • 4 replies
  • 1624 views

When porting applications from single core M4's equipped with FLASH, the RAM associated with M4 in MP1 is supposed to cater for both RAM and former FLASH needs. It won't fit. How to overcome this if M4 code/data size cannot be reduced?

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    4 replies

    Graduate II
    October 26, 2020

    How much do you actually need?

    It should have S-Bus access to other memories in the system on the A7 side. Should be able to page or overlay

    PeterLAuthor
    Graduate
    October 26, 2020

    512 kB would be sufficient for code.

    Technical Moderator
    October 27, 2020

    There is 448KBytes on Cortex-M4 side. Usually, as M4 side does not embed complex protocol stack or display/graphic (which are devoted to be handled by Linux), there is enough room for complex 'coprocessor' usages. apart optimization, one way to reduce code/data requirements is to move more processing up to Linux side (whenever possible). Maybe look at https://wiki.st.com/stm32mpu/wiki/How_to_exchange_large_data_buffers_with_the_coprocessor_-_principle

    System wise, DDR is not accessible from M4 side as this will end-up to complex Linux memory management issue as well as performance penalty on both M4 and Linux side (due to non-optimized transfers from M4 as there is no cache nor accelerator).

    For some extended data storage, there is option to add an external SRAM on FMC (this choice is exclusive of Linux NAND usage on FMC). Performance is not best, but might work, depending on your application requirements.

    Regards

    PeterLAuthor
    Graduate
    October 27, 2020

    Just to clarify on M4 application. No protocol stack nor display is used. The code set is certified and may not be transferred in parts to A7-side. It must be standalone from linux alltogether since it must boot within 2 seconds and be able to run during linux upgrade and so on. Linux "just" adds display and comm stacks to the selfcontained M4 application.

    The idea was to remake our two discrete nodes into a dual core, but it seems hard due to memory constraints. No simple dual core transition path. Minimum 350 kB code + 256 kB RAM required. Performance requirements does not allow for any slower memories involved.

    Explorer II
    August 10, 2023

    Hi Peter! Could you solve this issue? Did you find a way to expand the cortexm4 memory?

    Thanks!